gpu: nvgpu: gm20b: Fix MISRA 15.6 violations

This fixes errors due to single statement loop bodies without braces,
which is part of Rule 15.6 of MISRA. This patch covers gpu/nvgpu/gm20b/

JIRA NVGPU-989

Change-Id: Ia177bd990409500fc8e8a2a54ba013df84cb9822
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1788050
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 96262934..73db1ae9 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -123,8 +123,9 @@ void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
                 nvgpu_err(g, "mmu fault timeout");
 
         /* release mmu fault trigger */
-        for_each_set_bit(engine_id, &engine_ids, 32)
+        for_each_set_bit(engine_id, &engine_ids, 32) {
                 gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0);
+        }
 }
 
 u32 gm20b_fifo_get_num_fifos(struct gk20a *g)