From 9b9a54920511d560d114881a923437fb88deffad Mon Sep 17 00:00:00 2001 From: Srirangan Date: Sat, 28 Jul 2018 23:09:45 +0530 Subject: gpu: nvgpu: gm20b: Fix MISRA 15.6 violations This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers gpu/nvgpu/gm20b/ JIRA NVGPU-989 Change-Id: Ia177bd990409500fc8e8a2a54ba013df84cb9822 Signed-off-by: Srirangan Reviewed-on: https://git-master.nvidia.com/r/1788050 Reviewed-by: svc-misra-checker Reviewed-by: Adeel Raza GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gm20b/fifo_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 96262934..73db1ae9 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -123,8 +123,9 @@ void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, nvgpu_err(g, "mmu fault timeout"); /* release mmu fault trigger */ - for_each_set_bit(engine_id, &engine_ids, 32) + for_each_set_bit(engine_id, &engine_ids, 32) { gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0); + } } u32 gm20b_fifo_get_num_fifos(struct gk20a *g) -- cgit v1.2.2