diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-09-20 12:44:26 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-22 09:14:02 -0400 |
commit | e32cc0108cf2ef5de7a17f0f6c0aa9af7faf23ed (patch) | |
tree | 9bd3cbc01e3b23387f58bb1e2fa7de54f6e450c1 /drivers/gpu/nvgpu/gm20b/fb_gm20b.c | |
parent | 2197a928c38ae8d518ad18348c7c2106fb56e230 (diff) |
gpu: nvgpu: read WPR info from fb
- Added function to read WPR info from FB
MMU registers
- Added HAL to point wpr info read function
- Replaced wpr info read from MC with HAL
- Removed debugfs header include from acr files.
JIRA NVGPU-128
Change-Id: I5ebec46bfe03b9200f2aa569f2e5a780a715616d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1564683
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/fb_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fb_gm20b.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c index 31947ad0..8f124eec 100644 --- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> | 24 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> |
25 | 25 | ||
26 | #define VPR_INFO_FETCH_WAIT (5) | 26 | #define VPR_INFO_FETCH_WAIT (5) |
27 | #define WPR_INFO_ADDR_ALIGNMENT 0x0000000c | ||
27 | 28 | ||
28 | void fb_gm20b_init_fs_state(struct gk20a *g) | 29 | void fb_gm20b_init_fs_state(struct gk20a *g) |
29 | { | 30 | { |
@@ -523,6 +524,37 @@ int gm20b_fb_vpr_info_fetch(struct gk20a *g) | |||
523 | return gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT); | 524 | return gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT); |
524 | } | 525 | } |
525 | 526 | ||
527 | void gm20b_fb_read_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) | ||
528 | { | ||
529 | u32 val = 0; | ||
530 | u64 wpr_start = 0; | ||
531 | u64 wpr_end = 0; | ||
532 | |||
533 | val = gk20a_readl(g, fb_mmu_wpr_info_r()); | ||
534 | val &= ~0xF; | ||
535 | val |= fb_mmu_wpr_info_index_wpr1_addr_lo_v(); | ||
536 | gk20a_writel(g, fb_mmu_wpr_info_r(), val); | ||
537 | |||
538 | val = gk20a_readl(g, fb_mmu_wpr_info_r()) >> 0x4; | ||
539 | wpr_start = hi32_lo32_to_u64( | ||
540 | (val >> (32 - WPR_INFO_ADDR_ALIGNMENT)), | ||
541 | (val << WPR_INFO_ADDR_ALIGNMENT)); | ||
542 | |||
543 | val = gk20a_readl(g, fb_mmu_wpr_info_r()); | ||
544 | val &= ~0xF; | ||
545 | val |= fb_mmu_wpr_info_index_wpr1_addr_hi_v(); | ||
546 | gk20a_writel(g, fb_mmu_wpr_info_r(), val); | ||
547 | |||
548 | val = gk20a_readl(g, fb_mmu_wpr_info_r()) >> 0x4; | ||
549 | wpr_end = hi32_lo32_to_u64( | ||
550 | (val >> (32 - WPR_INFO_ADDR_ALIGNMENT)), | ||
551 | (val << WPR_INFO_ADDR_ALIGNMENT)); | ||
552 | |||
553 | inf->wpr_base = wpr_start; | ||
554 | inf->nonwpr_base = 0; | ||
555 | inf->size = (wpr_end - wpr_start); | ||
556 | } | ||
557 | |||
526 | bool gm20b_fb_debug_mode_enabled(struct gk20a *g) | 558 | bool gm20b_fb_debug_mode_enabled(struct gk20a *g) |
527 | { | 559 | { |
528 | u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | 560 | u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); |