From e32cc0108cf2ef5de7a17f0f6c0aa9af7faf23ed Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 20 Sep 2017 22:14:26 +0530 Subject: gpu: nvgpu: read WPR info from fb - Added function to read WPR info from FB MMU registers - Added HAL to point wpr info read function - Replaced wpr info read from MC with HAL - Removed debugfs header include from acr files. JIRA NVGPU-128 Change-Id: I5ebec46bfe03b9200f2aa569f2e5a780a715616d Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1564683 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gm20b/fb_gm20b.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/gpu/nvgpu/gm20b/fb_gm20b.c') diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c index 31947ad0..8f124eec 100644 --- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c @@ -24,6 +24,7 @@ #include #define VPR_INFO_FETCH_WAIT (5) +#define WPR_INFO_ADDR_ALIGNMENT 0x0000000c void fb_gm20b_init_fs_state(struct gk20a *g) { @@ -523,6 +524,37 @@ int gm20b_fb_vpr_info_fetch(struct gk20a *g) return gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT); } +void gm20b_fb_read_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) +{ + u32 val = 0; + u64 wpr_start = 0; + u64 wpr_end = 0; + + val = gk20a_readl(g, fb_mmu_wpr_info_r()); + val &= ~0xF; + val |= fb_mmu_wpr_info_index_wpr1_addr_lo_v(); + gk20a_writel(g, fb_mmu_wpr_info_r(), val); + + val = gk20a_readl(g, fb_mmu_wpr_info_r()) >> 0x4; + wpr_start = hi32_lo32_to_u64( + (val >> (32 - WPR_INFO_ADDR_ALIGNMENT)), + (val << WPR_INFO_ADDR_ALIGNMENT)); + + val = gk20a_readl(g, fb_mmu_wpr_info_r()); + val &= ~0xF; + val |= fb_mmu_wpr_info_index_wpr1_addr_hi_v(); + gk20a_writel(g, fb_mmu_wpr_info_r(), val); + + val = gk20a_readl(g, fb_mmu_wpr_info_r()) >> 0x4; + wpr_end = hi32_lo32_to_u64( + (val >> (32 - WPR_INFO_ADDR_ALIGNMENT)), + (val << WPR_INFO_ADDR_ALIGNMENT)); + + inf->wpr_base = wpr_start; + inf->nonwpr_base = 0; + inf->size = (wpr_end - wpr_start); +} + bool gm20b_fb_debug_mode_enabled(struct gk20a *g) { u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); -- cgit v1.2.2