gpu: nvgpu: gm20b expose gpcclk through CCF

Register gpcclk with Common Clock Framework to expose GPCPLL frequency
control

Bug 200233943

Change-Id: Id6f7bbaca15f22157b91b092c2a035af933fa71e
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1236979
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
index 84a2ce9a..7ea84826 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
@@ -21,10 +21,10 @@
 
 #include <linux/mutex.h>
 
-#ifdef CONFIG_TEGRA_CLK_FRAMEWORK
 void gm20b_init_clk_ops(struct gpu_ops *gops);
-#else
-static inline void gm20b_init_clk_ops(struct gpu_ops *gops) {}
+
+#ifdef CONFIG_COMMON_CLK
+int gm20b_register_gpcclk(struct gk20a *g);
 #endif
 
 #endif /* _NVHOST_CLK_GM20B_H_ */