From 01e61860fafbc0ee045c2db931a79f6c0d5300aa Mon Sep 17 00:00:00 2001 From: Peter Boonstoppel Date: Fri, 7 Oct 2016 15:30:59 -0700 Subject: gpu: nvgpu: gm20b expose gpcclk through CCF Register gpcclk with Common Clock Framework to expose GPCPLL frequency control Bug 200233943 Change-Id: Id6f7bbaca15f22157b91b092c2a035af933fa71e Signed-off-by: Peter Boonstoppel Reviewed-on: http://git-master/r/1236979 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/clk_gm20b.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gm20b/clk_gm20b.h') diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h index 84a2ce9a..7ea84826 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h @@ -21,10 +21,10 @@ #include -#ifdef CONFIG_TEGRA_CLK_FRAMEWORK void gm20b_init_clk_ops(struct gpu_ops *gops); -#else -static inline void gm20b_init_clk_ops(struct gpu_ops *gops) {} + +#ifdef CONFIG_COMMON_CLK +int gm20b_register_gpcclk(struct gk20a *g); #endif #endif /* _NVHOST_CLK_GM20B_H_ */ -- cgit v1.2.2