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authorTerje Bergstrom <tbergstrom@nvidia.com>2014-11-12 07:22:35 -0500
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:12:19 -0400
commit2d71d633cf754e15c5667215c44086080c7c328d (patch)
tree62e64ee0c4aa8128abc66fa83a66c1dd678965b3 /drivers/gpu/nvgpu/gm20b/acr_gm20b.c
parent1deb73b9c6512c6f0a296e35145c49233ea47f74 (diff)
gpu: nvgpu: Physical page bits to be per chip
Retrieve number of physical page bits based on chip. Bug 1567274 Change-Id: I5a0f6a66be37f2cf720d66b5bdb2b704cd992234 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/601700
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/acr_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/acr_gm20b.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 470a93bc..cb874a48 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -258,7 +258,8 @@ int prepare_ucode_blob(struct gk20a *g)
258 gm20b_dbg_pmu("managed LS falcon %d, WPR size %d bytes.\n", 258 gm20b_dbg_pmu("managed LS falcon %d, WPR size %d bytes.\n",
259 plsfm->managed_flcn_cnt, plsfm->wpr_size); 259 plsfm->managed_flcn_cnt, plsfm->wpr_size);
260 lsfm_init_wpr_contents(g, plsfm, nonwpr_addr); 260 lsfm_init_wpr_contents(g, plsfm, nonwpr_addr);
261 g->acr.ucode_blob_start = NV_MC_SMMU_VADDR_TRANSLATE(iova); 261 g->acr.ucode_blob_start =
262 gk20a_mm_smmu_vaddr_translate(g, iova);
262 g->acr.ucode_blob_size = plsfm->wpr_size; 263 g->acr.ucode_blob_size = plsfm->wpr_size;
263 gm20b_dbg_pmu("base reg carveout 2:%x\n", 264 gm20b_dbg_pmu("base reg carveout 2:%x\n",
264 readl(mc + MC_SECURITY_CARVEOUT2_BOM_0)); 265 readl(mc + MC_SECURITY_CARVEOUT2_BOM_0));