summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gm206
diff options
context:
space:
mode:
authorTerje Bergstrom <tbergstrom@nvidia.com>2017-02-08 17:11:17 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-02-17 16:46:32 -0500
commit6a58857b6517607b888090e6b87f3302ea8b2e97 (patch)
treec123405cfca9ef326a3594b39a9a9ce47b287511 /drivers/gpu/nvgpu/gm206
parent53465def649b813987ca0d4a7ced744305204b82 (diff)
gpu: nvgpu: Remove almost all gm204/gm206 support
Remove gm204/gm206 support. It was used only in the interim until Pascal cards were available, and we don't maintain that code anymore. This patch leaves only BIOS code. Change-Id: I215988603d4588ef710bdda6e47449e9235e78ac Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302224 GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gm206')
-rw-r--r--drivers/gpu/nvgpu/gm206/bios_gm206.c1
-rw-r--r--drivers/gpu/nvgpu/gm206/ce_gm206.c107
-rw-r--r--drivers/gpu/nvgpu/gm206/ce_gm206.h26
-rw-r--r--drivers/gpu/nvgpu/gm206/fifo_gm206.c35
-rw-r--r--drivers/gpu/nvgpu/gm206/fifo_gm206.h18
-rw-r--r--drivers/gpu/nvgpu/gm206/gr_gm206.c93
-rw-r--r--drivers/gpu/nvgpu/gm206/gr_gm206.h23
-rw-r--r--drivers/gpu/nvgpu/gm206/hal_gm206.c225
-rw-r--r--drivers/gpu/nvgpu/gm206/hal_gm206.h19
-rw-r--r--drivers/gpu/nvgpu/gm206/mm_gm206.c37
-rw-r--r--drivers/gpu/nvgpu/gm206/mm_gm206.h24
11 files changed, 0 insertions, 608 deletions
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c
index 3d12b9ac..6e20e23a 100644
--- a/drivers/gpu/nvgpu/gm206/bios_gm206.c
+++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c
@@ -20,7 +20,6 @@
20 20
21#include "gk20a/gk20a.h" 21#include "gk20a/gk20a.h"
22#include "gm20b/fifo_gm20b.h" 22#include "gm20b/fifo_gm20b.h"
23#include "fifo_gm206.h"
24#include "bios_gm206.h" 23#include "bios_gm206.h"
25 24
26#include <nvgpu/nvgpu_common.h> 25#include <nvgpu/nvgpu_common.h>
diff --git a/drivers/gpu/nvgpu/gm206/ce_gm206.c b/drivers/gpu/nvgpu/gm206/ce_gm206.c
deleted file mode 100644
index dd3eac95..00000000
--- a/drivers/gpu/nvgpu/gm206/ce_gm206.c
+++ /dev/null
@@ -1,107 +0,0 @@
1/*
2 * GM206 Copy Engine.
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.
17 */
18
19/*TODO: remove uncecessary */
20#include "gk20a/gk20a.h"
21#include "ce_gm206.h"
22
23/*TODO: remove uncecessary */
24#include <linux/delay.h>
25#include <linux/slab.h>
26#include <linux/scatterlist.h>
27#include <trace/events/gk20a.h>
28#include <linux/dma-mapping.h>
29#include <linux/nvhost.h>
30
31#include "gk20a/debug_gk20a.h"
32
33#include <nvgpu/hw/gm206/hw_ce2_gm206.h>
34#include <nvgpu/hw/gm206/hw_pbdma_gm206.h>
35#include <nvgpu/hw/gm206/hw_ccsr_gm206.h>
36#include <nvgpu/hw/gm206/hw_ram_gm206.h>
37#include <nvgpu/hw/gm206/hw_top_gm206.h>
38#include <nvgpu/hw/gm206/hw_mc_gm206.h>
39#include <nvgpu/hw/gm206/hw_gr_gm206.h>
40
41/* TODO: We need generic way for query the intr_status register offset.
42 * As of now, there is no way to query this information from dev_ceN_pri.h */
43#define COP_INTR_STATUS_OFFSET 0x908
44
45static u32 ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id)
46{
47 gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n");
48
49 return ce2_intr_status_nonblockpipe_pending_f();
50}
51
52static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id)
53{
54 gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n");
55
56 return ce2_intr_status_blockpipe_pending_f();
57}
58
59static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id)
60{
61 gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n");
62
63 return ce2_intr_status_launcherr_pending_f();
64}
65
66static void gm206_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
67{
68 u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET);
69 u32 ce_intr = gk20a_readl(g, ce_intr_status_reg);
70 u32 clear_intr = 0;
71
72 gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id);
73
74 /* clear blocking interrupts: they exibit broken behavior */
75 if (ce_intr & ce2_intr_status_blockpipe_pending_f())
76 clear_intr |= ce_blockpipe_isr(g, ce_intr, inst_id);
77
78 if (ce_intr & ce2_intr_status_launcherr_pending_f())
79 clear_intr |= ce_launcherr_isr(g, ce_intr, inst_id);
80
81 gk20a_writel(g, ce_intr_status_reg, clear_intr);
82 return;
83}
84
85static void gm206_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
86{
87 u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET);
88 u32 ce_intr = gk20a_readl(g, ce_intr_status_reg);
89
90 gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id);
91
92 if (ce_intr & ce2_intr_status_nonblockpipe_pending_f()) {
93 gk20a_writel(g, ce_intr_status_reg,
94 ce_nonblockpipe_isr(g, ce_intr, inst_id));
95
96 /* wake threads waiting in this channel */
97 gk20a_channel_semaphore_wakeup(g, true);
98 }
99
100 return;
101}
102
103void gm206_init_ce(struct gpu_ops *gops)
104{
105 gops->ce2.isr_stall = gm206_ce_isr;
106 gops->ce2.isr_nonstall = gm206_ce_nonstall_isr;
107}
diff --git a/drivers/gpu/nvgpu/gm206/ce_gm206.h b/drivers/gpu/nvgpu/gm206/ce_gm206.h
deleted file mode 100644
index c2fb1586..00000000
--- a/drivers/gpu/nvgpu/gm206/ce_gm206.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * GM206 copy engine.
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program.
17 */
18#ifndef __CE_GM206_H__
19#define __CE_GM206_H__
20
21#include "gk20a/channel_gk20a.h"
22#include "gk20a/tsg_gk20a.h"
23
24void gm206_init_ce(struct gpu_ops *gops);
25
26#endif /*__CE2_GM20B_H__*/
diff --git a/drivers/gpu/nvgpu/gm206/fifo_gm206.c b/drivers/gpu/nvgpu/gm206/fifo_gm206.c
deleted file mode 100644
index 01fb2f82..00000000
--- a/drivers/gpu/nvgpu/gm206/fifo_gm206.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/delay.h>
15#include <linux/types.h>
16
17#include "fifo_gm206.h"
18
19#include "gk20a/gk20a.h"
20#include "gm20b/fifo_gm20b.h"
21
22#include <nvgpu/hw/gm206/hw_ccsr_gm206.h>
23#include <nvgpu/hw/gm206/hw_fifo_gm206.h>
24
25static u32 gm206_fifo_get_num_fifos(struct gk20a *g)
26{
27 return ccsr_channel__size_1_v();
28}
29
30void gm206_init_fifo(struct gpu_ops *gops)
31{
32 gm20b_init_fifo(gops);
33 gops->fifo.get_num_fifos = gm206_fifo_get_num_fifos;
34 gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
35}
diff --git a/drivers/gpu/nvgpu/gm206/fifo_gm206.h b/drivers/gpu/nvgpu/gm206/fifo_gm206.h
deleted file mode 100644
index 5cad0e8a..00000000
--- a/drivers/gpu/nvgpu/gm206/fifo_gm206.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef NVGPU_FIFO_GM206_H
15#define NVGPU_FIFO_GM206_H
16struct gpu_ops;
17void gm206_init_fifo(struct gpu_ops *gops);
18#endif
diff --git a/drivers/gpu/nvgpu/gm206/gr_gm206.c b/drivers/gpu/nvgpu/gm206/gr_gm206.c
deleted file mode 100644
index b7956eca..00000000
--- a/drivers/gpu/nvgpu/gm206/gr_gm206.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * gm206 GR
3 *
4 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/types.h>
17#include <linux/delay.h> /* for mdelay */
18#include <linux/io.h>
19#include <linux/vmalloc.h>
20#include <soc/tegra/fuse.h>
21
22#include "gk20a/gk20a.h"
23
24#include "gm20b/gr_gm20b.h"
25#include "gr_gm206.h"
26
27#include <nvgpu/hw/gm206/hw_fb_gm206.h>
28#include <nvgpu/hw/gm206/hw_gr_gm206.h>
29
30static void gr_gm206_init_gpc_mmu(struct gk20a *g)
31{
32 u32 temp;
33
34 gk20a_dbg_info("initialize gpc mmu");
35
36 temp = gk20a_readl(g, fb_mmu_ctrl_r());
37 temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() |
38 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() |
39 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() |
40 gr_gpcs_pri_mmu_ctrl_vol_fault_m() |
41 gr_gpcs_pri_mmu_ctrl_comp_fault_m() |
42 gr_gpcs_pri_mmu_ctrl_miss_gran_m() |
43 gr_gpcs_pri_mmu_ctrl_cache_mode_m() |
44 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() |
45 gr_gpcs_pri_mmu_ctrl_mmu_vol_m() |
46 gr_gpcs_pri_mmu_ctrl_mmu_disable_m();
47 gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp);
48 gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0);
49 gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0);
50
51 gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(),
52 gk20a_readl(g, fb_mmu_debug_ctrl_r()));
53 gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(),
54 gk20a_readl(g, fb_mmu_debug_wr_r()));
55 gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(),
56 gk20a_readl(g, fb_mmu_debug_rd_r()));
57
58 gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(),
59 gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
60 /* TODO: num_active_ltcs2! */
61 gk20a_writel(g, 0x50833c, gk20a_readl(g, 0x100804));
62}
63
64static void gr_gm206_bundle_cb_defaults(struct gk20a *g)
65{
66 struct gr_gk20a *gr = &g->gr;
67
68 gr->bundle_cb_default_size =
69 gr_scc_bundle_cb_size_div_256b__prod_v();
70 gr->min_gpm_fifo_depth =
71 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v();
72 gr->bundle_cb_token_limit =
73 gr_pd_ab_dist_cfg2_token_limit_init_v();
74}
75
76static void gr_gm206_cb_size_default(struct gk20a *g)
77{
78 struct gr_gk20a *gr = &g->gr;
79
80 if (!gr->attrib_cb_default_size)
81 gr->attrib_cb_default_size =
82 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v();
83 gr->alpha_cb_default_size =
84 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
85}
86
87void gm206_init_gr(struct gpu_ops *gops)
88{
89 gm20b_init_gr(gops);
90 gops->gr.init_gpc_mmu = gr_gm206_init_gpc_mmu;
91 gops->gr.bundle_cb_defaults = gr_gm206_bundle_cb_defaults;
92 gops->gr.cb_size_default = gr_gm206_cb_size_default;
93}
diff --git a/drivers/gpu/nvgpu/gm206/gr_gm206.h b/drivers/gpu/nvgpu/gm206/gr_gm206.h
deleted file mode 100644
index 740685e8..00000000
--- a/drivers/gpu/nvgpu/gm206/gr_gm206.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * GM206 GR
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_GM206_GR_H
17#define _NVGPU_GM206_GR_H
18
19struct gpu_ops;
20
21void gm206_init_gr(struct gpu_ops *gops);
22
23#endif
diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.c b/drivers/gpu/nvgpu/gm206/hal_gm206.c
deleted file mode 100644
index e2b84d81..00000000
--- a/drivers/gpu/nvgpu/gm206/hal_gm206.c
+++ /dev/null
@@ -1,225 +0,0 @@
1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/types.h>
15#include <linux/printk.h>
16#include <linux/types.h>
17
18#include "ce_gm206.h"
19#include "fifo_gm206.h"
20#include "bios_gm206.h"
21#include "gr_gm206.h"
22
23#include "gk20a/gk20a.h"
24#include "gk20a/dbg_gpu_gk20a.h"
25#include "gk20a/css_gr_gk20a.h"
26#include "gm20b/mc_gm20b.h"
27#include "gm20b/ltc_gm20b.h"
28#include "gm20b/mm_gm20b.h"
29#include "gm20b/fb_gm20b.h"
30#include "gm20b/pmu_gm20b.h"
31#include "gm20b/gr_gm20b.h"
32#include "gm20b/gr_ctx_gm20b.h"
33#include "gm20b/gm20b_gating_reglist.h"
34#include "gm20b/regops_gm20b.h"
35#include "gm20b/cde_gm20b.h"
36#include "gm20b/therm_gm20b.h"
37#include "gm20b/clk_gm20b.h"
38#include "gm20b/debug_gm20b.h"
39#include "gm206/mm_gm206.h"
40
41#include <nvgpu/hw/gm206/hw_proj_gm206.h>
42
43static struct gpu_ops gm206_ops = {
44 .clock_gating = {
45 .slcg_bus_load_gating_prod =
46 gm20b_slcg_bus_load_gating_prod,
47 .slcg_ce2_load_gating_prod =
48 gm20b_slcg_ce2_load_gating_prod,
49 .slcg_chiplet_load_gating_prod =
50 gm20b_slcg_chiplet_load_gating_prod,
51 .slcg_ctxsw_firmware_load_gating_prod =
52 gm20b_slcg_ctxsw_firmware_load_gating_prod,
53 .slcg_fb_load_gating_prod =
54 gm20b_slcg_fb_load_gating_prod,
55 .slcg_fifo_load_gating_prod =
56 gm20b_slcg_fifo_load_gating_prod,
57 .slcg_gr_load_gating_prod =
58 gr_gm20b_slcg_gr_load_gating_prod,
59 .slcg_ltc_load_gating_prod =
60 ltc_gm20b_slcg_ltc_load_gating_prod,
61 .slcg_perf_load_gating_prod =
62 gm20b_slcg_perf_load_gating_prod,
63 .slcg_priring_load_gating_prod =
64 gm20b_slcg_priring_load_gating_prod,
65 .slcg_pmu_load_gating_prod =
66 gm20b_slcg_pmu_load_gating_prod,
67 .slcg_therm_load_gating_prod =
68 gm20b_slcg_therm_load_gating_prod,
69 .slcg_xbar_load_gating_prod =
70 gm20b_slcg_xbar_load_gating_prod,
71 .blcg_bus_load_gating_prod =
72 gm20b_blcg_bus_load_gating_prod,
73 .blcg_ctxsw_firmware_load_gating_prod =
74 gm20b_blcg_ctxsw_firmware_load_gating_prod,
75 .blcg_fb_load_gating_prod =
76 gm20b_blcg_fb_load_gating_prod,
77 .blcg_fifo_load_gating_prod =
78 gm20b_blcg_fifo_load_gating_prod,
79 .blcg_gr_load_gating_prod =
80 gm20b_blcg_gr_load_gating_prod,
81 .blcg_ltc_load_gating_prod =
82 gm20b_blcg_ltc_load_gating_prod,
83 .blcg_pwr_csb_load_gating_prod =
84 gm20b_blcg_pwr_csb_load_gating_prod,
85 .blcg_pmu_load_gating_prod =
86 gm20b_blcg_pmu_load_gating_prod,
87 .blcg_xbar_load_gating_prod =
88 gm20b_blcg_xbar_load_gating_prod,
89 .pg_gr_load_gating_prod =
90 gr_gm20b_pg_gr_load_gating_prod,
91 }
92};
93
94static int gm206_get_litter_value(struct gk20a *g, int value)
95{
96 int ret = -EINVAL;
97
98 switch (value) {
99 case GPU_LIT_NUM_GPCS:
100 ret = proj_scal_litter_num_gpcs_v();
101 break;
102 case GPU_LIT_NUM_PES_PER_GPC:
103 ret = proj_scal_litter_num_pes_per_gpc_v();
104 break;
105 case GPU_LIT_NUM_ZCULL_BANKS:
106 ret = proj_scal_litter_num_zcull_banks_v();
107 break;
108 case GPU_LIT_NUM_TPC_PER_GPC:
109 ret = proj_scal_litter_num_tpc_per_gpc_v();
110 break;
111 case GPU_LIT_NUM_FBPS:
112 ret = proj_scal_litter_num_fbps_v();
113 break;
114 case GPU_LIT_GPC_BASE:
115 ret = proj_gpc_base_v();
116 break;
117 case GPU_LIT_GPC_STRIDE:
118 ret = proj_gpc_stride_v();
119 break;
120 case GPU_LIT_GPC_SHARED_BASE:
121 ret = proj_gpc_shared_base_v();
122 break;
123 case GPU_LIT_TPC_IN_GPC_BASE:
124 ret = proj_tpc_in_gpc_base_v();
125 break;
126 case GPU_LIT_TPC_IN_GPC_STRIDE:
127 ret = proj_tpc_in_gpc_stride_v();
128 break;
129 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
130 ret = proj_tpc_in_gpc_shared_base_v();
131 break;
132 case GPU_LIT_PPC_IN_GPC_STRIDE:
133 ret = proj_ppc_in_gpc_stride_v();
134 break;
135 case GPU_LIT_ROP_BASE:
136 ret = proj_rop_base_v();
137 break;
138 case GPU_LIT_ROP_STRIDE:
139 ret = proj_rop_stride_v();
140 break;
141 case GPU_LIT_ROP_SHARED_BASE:
142 ret = proj_rop_shared_base_v();
143 break;
144 case GPU_LIT_HOST_NUM_ENGINES:
145 ret = proj_host_num_engines_v();
146 break;
147 case GPU_LIT_HOST_NUM_PBDMA:
148 ret = proj_host_num_pbdma_v();
149 break;
150 case GPU_LIT_LTC_STRIDE:
151 ret = proj_ltc_stride_v();
152 break;
153 case GPU_LIT_LTS_STRIDE:
154 ret = proj_lts_stride_v();
155 break;
156 case GPU_LIT_NUM_FBPAS:
157 ret = proj_scal_litter_num_fbpas_v();
158 break;
159 case GPU_LIT_FBPA_STRIDE:
160 ret = proj_fbpa_stride_v();
161 break;
162 default:
163 BUG();
164 break;
165 }
166
167 return ret;
168}
169
170int gm206_init_hal(struct gk20a *g)
171{
172 struct gpu_ops *gops = &g->ops;
173 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
174 u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
175
176 *gops = gm206_ops;
177
178 gops->privsecurity = 1;
179 gops->securegpccs = 1;
180 gops->pmupstate = false;
181 gm20b_init_mc(gops);
182 gm20b_init_ltc(gops);
183 gm206_init_gr(gops);
184 gm20b_init_ltc(gops);
185 gm20b_init_fb(gops);
186 g->ops.fb.set_use_full_comp_tag_line = NULL;
187 gm206_init_fifo(gops);
188 gm206_init_ce(gops);
189 gm20b_init_gr_ctx(gops);
190 gm206_init_mm(gops);
191 gm20b_init_clk_ops(gops);
192 gm20b_init_regops(gops);
193 gm20b_init_debug_ops(gops);
194 gk20a_init_dbg_session_ops(gops);
195 gm20b_init_cde_ops(gops);
196 gm20b_init_therm_ops(gops);
197 gk20a_init_tsg_ops(gops);
198#if defined(CONFIG_GK20A_CYCLE_STATS)
199 gk20a_init_css_ops(gops);
200#endif
201 gm206_init_bios_ops(gops);
202 switch(ver){
203 case GK20A_GPUID_GM206:
204 gops->name = "gm206";
205 break;
206 case GK20A_GPUID_GM204:
207 gops->name = "gm204";
208 break;
209 default:
210 gk20a_err(g->dev, "no support for %x", ver);
211 BUG();
212 }
213 gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
214 gops->get_litter_value = gm206_get_litter_value;
215 gops->gr_ctx.use_dma_for_fw_bootstrap = true;
216
217 c->twod_class = FERMI_TWOD_A;
218 c->threed_class = MAXWELL_B;
219 c->compute_class = MAXWELL_COMPUTE_B;
220 c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A;
221 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
222 c->dma_copy_class = MAXWELL_DMA_COPY_A;
223
224 return 0;
225}
diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.h b/drivers/gpu/nvgpu/gm206/hal_gm206.h
deleted file mode 100644
index b7fab24c..00000000
--- a/drivers/gpu/nvgpu/gm206/hal_gm206.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef _NVGPU_HAL_GM206_H
15#define _NVGPU_HAL_GM206_H
16struct gk20a;
17
18int gm206_init_hal(struct gk20a *gops);
19#endif
diff --git a/drivers/gpu/nvgpu/gm206/mm_gm206.c b/drivers/gpu/nvgpu/gm206/mm_gm206.c
deleted file mode 100644
index 75c8a234..00000000
--- a/drivers/gpu/nvgpu/gm206/mm_gm206.c
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * GM206 memory management
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include "gk20a/gk20a.h"
17#include "gm20b/mm_gm20b.h"
18#include "gm206/mm_gm206.h"
19
20#include <nvgpu/hw/gm206/hw_fbpa_gm206.h>
21#include <nvgpu/hw/gm206/hw_top_gm206.h>
22
23static size_t gm206_mm_get_vidmem_size(struct gk20a *g)
24{
25 u32 fbpas = top_num_fbpas_value_v(
26 gk20a_readl(g, top_num_fbpas_r()));
27 u32 ram = fbpa_cstatus_ramamount_v(
28 gk20a_readl(g, fbpa_cstatus_r()));
29 return (size_t)fbpas * ram * SZ_1M;
30}
31
32void gm206_init_mm(struct gpu_ops *gops)
33{
34 gm20b_init_mm(gops);
35 gops->mm.get_vidmem_size = gm206_mm_get_vidmem_size;
36 gops->mm.get_physical_addr_bits = NULL;
37}
diff --git a/drivers/gpu/nvgpu/gm206/mm_gm206.h b/drivers/gpu/nvgpu/gm206/mm_gm206.h
deleted file mode 100644
index 60aa6fe4..00000000
--- a/drivers/gpu/nvgpu/gm206/mm_gm206.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * GM206 memory management
3 *
4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef MM_GM206_H
17#define MM_GM206_H
18
19struct gpu_ops;
20
21void gm206_init_mm(struct gpu_ops *gops);
22
23#endif
24
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-02 20:50:07 -0400