From 6a58857b6517607b888090e6b87f3302ea8b2e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 8 Feb 2017 14:11:17 -0800 Subject: gpu: nvgpu: Remove almost all gm204/gm206 support Remove gm204/gm206 support. It was used only in the interim until Pascal cards were available, and we don't maintain that code anymore. This patch leaves only BIOS code. Change-Id: I215988603d4588ef710bdda6e47449e9235e78ac Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1302224 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gm206/bios_gm206.c | 1 - drivers/gpu/nvgpu/gm206/ce_gm206.c | 107 ----------------- drivers/gpu/nvgpu/gm206/ce_gm206.h | 26 ---- drivers/gpu/nvgpu/gm206/fifo_gm206.c | 35 ------ drivers/gpu/nvgpu/gm206/fifo_gm206.h | 18 --- drivers/gpu/nvgpu/gm206/gr_gm206.c | 93 --------------- drivers/gpu/nvgpu/gm206/gr_gm206.h | 23 ---- drivers/gpu/nvgpu/gm206/hal_gm206.c | 225 ----------------------------------- drivers/gpu/nvgpu/gm206/hal_gm206.h | 19 --- drivers/gpu/nvgpu/gm206/mm_gm206.c | 37 ------ drivers/gpu/nvgpu/gm206/mm_gm206.h | 24 ---- 11 files changed, 608 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gm206/ce_gm206.c delete mode 100644 drivers/gpu/nvgpu/gm206/ce_gm206.h delete mode 100644 drivers/gpu/nvgpu/gm206/fifo_gm206.c delete mode 100644 drivers/gpu/nvgpu/gm206/fifo_gm206.h delete mode 100644 drivers/gpu/nvgpu/gm206/gr_gm206.c delete mode 100644 drivers/gpu/nvgpu/gm206/gr_gm206.h delete mode 100644 drivers/gpu/nvgpu/gm206/hal_gm206.c delete mode 100644 drivers/gpu/nvgpu/gm206/hal_gm206.h delete mode 100644 drivers/gpu/nvgpu/gm206/mm_gm206.c delete mode 100644 drivers/gpu/nvgpu/gm206/mm_gm206.h (limited to 'drivers/gpu/nvgpu/gm206') diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c index 3d12b9ac..6e20e23a 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.c +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c @@ -20,7 +20,6 @@ #include "gk20a/gk20a.h" #include "gm20b/fifo_gm20b.h" -#include "fifo_gm206.h" #include "bios_gm206.h" #include diff --git a/drivers/gpu/nvgpu/gm206/ce_gm206.c b/drivers/gpu/nvgpu/gm206/ce_gm206.c deleted file mode 100644 index dd3eac95..00000000 --- a/drivers/gpu/nvgpu/gm206/ce_gm206.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * GM206 Copy Engine. - * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. - */ - -/*TODO: remove uncecessary */ -#include "gk20a/gk20a.h" -#include "ce_gm206.h" - -/*TODO: remove uncecessary */ -#include -#include -#include -#include -#include -#include - -#include "gk20a/debug_gk20a.h" - -#include -#include -#include -#include -#include -#include -#include - -/* TODO: We need generic way for query the intr_status register offset. - * As of now, there is no way to query this information from dev_ceN_pri.h */ -#define COP_INTR_STATUS_OFFSET 0x908 - -static u32 ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) -{ - gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n"); - - return ce2_intr_status_nonblockpipe_pending_f(); -} - -static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) -{ - gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n"); - - return ce2_intr_status_blockpipe_pending_f(); -} - -static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) -{ - gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n"); - - return ce2_intr_status_launcherr_pending_f(); -} - -static void gm206_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) -{ - u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET); - u32 ce_intr = gk20a_readl(g, ce_intr_status_reg); - u32 clear_intr = 0; - - gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); - - /* clear blocking interrupts: they exibit broken behavior */ - if (ce_intr & ce2_intr_status_blockpipe_pending_f()) - clear_intr |= ce_blockpipe_isr(g, ce_intr, inst_id); - - if (ce_intr & ce2_intr_status_launcherr_pending_f()) - clear_intr |= ce_launcherr_isr(g, ce_intr, inst_id); - - gk20a_writel(g, ce_intr_status_reg, clear_intr); - return; -} - -static void gm206_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) -{ - u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET); - u32 ce_intr = gk20a_readl(g, ce_intr_status_reg); - - gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); - - if (ce_intr & ce2_intr_status_nonblockpipe_pending_f()) { - gk20a_writel(g, ce_intr_status_reg, - ce_nonblockpipe_isr(g, ce_intr, inst_id)); - - /* wake threads waiting in this channel */ - gk20a_channel_semaphore_wakeup(g, true); - } - - return; -} - -void gm206_init_ce(struct gpu_ops *gops) -{ - gops->ce2.isr_stall = gm206_ce_isr; - gops->ce2.isr_nonstall = gm206_ce_nonstall_isr; -} diff --git a/drivers/gpu/nvgpu/gm206/ce_gm206.h b/drivers/gpu/nvgpu/gm206/ce_gm206.h deleted file mode 100644 index c2fb1586..00000000 --- a/drivers/gpu/nvgpu/gm206/ce_gm206.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * GM206 copy engine. - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. - */ -#ifndef __CE_GM206_H__ -#define __CE_GM206_H__ - -#include "gk20a/channel_gk20a.h" -#include "gk20a/tsg_gk20a.h" - -void gm206_init_ce(struct gpu_ops *gops); - -#endif /*__CE2_GM20B_H__*/ diff --git a/drivers/gpu/nvgpu/gm206/fifo_gm206.c b/drivers/gpu/nvgpu/gm206/fifo_gm206.c deleted file mode 100644 index 01fb2f82..00000000 --- a/drivers/gpu/nvgpu/gm206/fifo_gm206.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include - -#include "fifo_gm206.h" - -#include "gk20a/gk20a.h" -#include "gm20b/fifo_gm20b.h" - -#include -#include - -static u32 gm206_fifo_get_num_fifos(struct gk20a *g) -{ - return ccsr_channel__size_1_v(); -} - -void gm206_init_fifo(struct gpu_ops *gops) -{ - gm20b_init_fifo(gops); - gops->fifo.get_num_fifos = gm206_fifo_get_num_fifos; - gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; -} diff --git a/drivers/gpu/nvgpu/gm206/fifo_gm206.h b/drivers/gpu/nvgpu/gm206/fifo_gm206.h deleted file mode 100644 index 5cad0e8a..00000000 --- a/drivers/gpu/nvgpu/gm206/fifo_gm206.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef NVGPU_FIFO_GM206_H -#define NVGPU_FIFO_GM206_H -struct gpu_ops; -void gm206_init_fifo(struct gpu_ops *gops); -#endif diff --git a/drivers/gpu/nvgpu/gm206/gr_gm206.c b/drivers/gpu/nvgpu/gm206/gr_gm206.c deleted file mode 100644 index b7956eca..00000000 --- a/drivers/gpu/nvgpu/gm206/gr_gm206.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * gm206 GR - * - * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include /* for mdelay */ -#include -#include -#include - -#include "gk20a/gk20a.h" - -#include "gm20b/gr_gm20b.h" -#include "gr_gm206.h" - -#include -#include - -static void gr_gm206_init_gpc_mmu(struct gk20a *g) -{ - u32 temp; - - gk20a_dbg_info("initialize gpc mmu"); - - temp = gk20a_readl(g, fb_mmu_ctrl_r()); - temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | - gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | - gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m() | - gr_gpcs_pri_mmu_ctrl_vol_fault_m() | - gr_gpcs_pri_mmu_ctrl_comp_fault_m() | - gr_gpcs_pri_mmu_ctrl_miss_gran_m() | - gr_gpcs_pri_mmu_ctrl_cache_mode_m() | - gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() | - gr_gpcs_pri_mmu_ctrl_mmu_vol_m() | - gr_gpcs_pri_mmu_ctrl_mmu_disable_m(); - gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp); - gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0); - gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); - - gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), - gk20a_readl(g, fb_mmu_debug_ctrl_r())); - gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(), - gk20a_readl(g, fb_mmu_debug_wr_r())); - gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), - gk20a_readl(g, fb_mmu_debug_rd_r())); - - gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(), - gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); - /* TODO: num_active_ltcs2! */ - gk20a_writel(g, 0x50833c, gk20a_readl(g, 0x100804)); -} - -static void gr_gm206_bundle_cb_defaults(struct gk20a *g) -{ - struct gr_gk20a *gr = &g->gr; - - gr->bundle_cb_default_size = - gr_scc_bundle_cb_size_div_256b__prod_v(); - gr->min_gpm_fifo_depth = - gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(); - gr->bundle_cb_token_limit = - gr_pd_ab_dist_cfg2_token_limit_init_v(); -} - -static void gr_gm206_cb_size_default(struct gk20a *g) -{ - struct gr_gk20a *gr = &g->gr; - - if (!gr->attrib_cb_default_size) - gr->attrib_cb_default_size = - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); - gr->alpha_cb_default_size = - gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); -} - -void gm206_init_gr(struct gpu_ops *gops) -{ - gm20b_init_gr(gops); - gops->gr.init_gpc_mmu = gr_gm206_init_gpc_mmu; - gops->gr.bundle_cb_defaults = gr_gm206_bundle_cb_defaults; - gops->gr.cb_size_default = gr_gm206_cb_size_default; -} diff --git a/drivers/gpu/nvgpu/gm206/gr_gm206.h b/drivers/gpu/nvgpu/gm206/gr_gm206.h deleted file mode 100644 index 740685e8..00000000 --- a/drivers/gpu/nvgpu/gm206/gr_gm206.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * GM206 GR - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _NVGPU_GM206_GR_H -#define _NVGPU_GM206_GR_H - -struct gpu_ops; - -void gm206_init_gr(struct gpu_ops *gops); - -#endif diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.c b/drivers/gpu/nvgpu/gm206/hal_gm206.c deleted file mode 100644 index e2b84d81..00000000 --- a/drivers/gpu/nvgpu/gm206/hal_gm206.c +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include -#include - -#include "ce_gm206.h" -#include "fifo_gm206.h" -#include "bios_gm206.h" -#include "gr_gm206.h" - -#include "gk20a/gk20a.h" -#include "gk20a/dbg_gpu_gk20a.h" -#include "gk20a/css_gr_gk20a.h" -#include "gm20b/mc_gm20b.h" -#include "gm20b/ltc_gm20b.h" -#include "gm20b/mm_gm20b.h" -#include "gm20b/fb_gm20b.h" -#include "gm20b/pmu_gm20b.h" -#include "gm20b/gr_gm20b.h" -#include "gm20b/gr_ctx_gm20b.h" -#include "gm20b/gm20b_gating_reglist.h" -#include "gm20b/regops_gm20b.h" -#include "gm20b/cde_gm20b.h" -#include "gm20b/therm_gm20b.h" -#include "gm20b/clk_gm20b.h" -#include "gm20b/debug_gm20b.h" -#include "gm206/mm_gm206.h" - -#include - -static struct gpu_ops gm206_ops = { - .clock_gating = { - .slcg_bus_load_gating_prod = - gm20b_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gm20b_slcg_ce2_load_gating_prod, - .slcg_chiplet_load_gating_prod = - gm20b_slcg_chiplet_load_gating_prod, - .slcg_ctxsw_firmware_load_gating_prod = - gm20b_slcg_ctxsw_firmware_load_gating_prod, - .slcg_fb_load_gating_prod = - gm20b_slcg_fb_load_gating_prod, - .slcg_fifo_load_gating_prod = - gm20b_slcg_fifo_load_gating_prod, - .slcg_gr_load_gating_prod = - gr_gm20b_slcg_gr_load_gating_prod, - .slcg_ltc_load_gating_prod = - ltc_gm20b_slcg_ltc_load_gating_prod, - .slcg_perf_load_gating_prod = - gm20b_slcg_perf_load_gating_prod, - .slcg_priring_load_gating_prod = - gm20b_slcg_priring_load_gating_prod, - .slcg_pmu_load_gating_prod = - gm20b_slcg_pmu_load_gating_prod, - .slcg_therm_load_gating_prod = - gm20b_slcg_therm_load_gating_prod, - .slcg_xbar_load_gating_prod = - gm20b_slcg_xbar_load_gating_prod, - .blcg_bus_load_gating_prod = - gm20b_blcg_bus_load_gating_prod, - .blcg_ctxsw_firmware_load_gating_prod = - gm20b_blcg_ctxsw_firmware_load_gating_prod, - .blcg_fb_load_gating_prod = - gm20b_blcg_fb_load_gating_prod, - .blcg_fifo_load_gating_prod = - gm20b_blcg_fifo_load_gating_prod, - .blcg_gr_load_gating_prod = - gm20b_blcg_gr_load_gating_prod, - .blcg_ltc_load_gating_prod = - gm20b_blcg_ltc_load_gating_prod, - .blcg_pwr_csb_load_gating_prod = - gm20b_blcg_pwr_csb_load_gating_prod, - .blcg_pmu_load_gating_prod = - gm20b_blcg_pmu_load_gating_prod, - .blcg_xbar_load_gating_prod = - gm20b_blcg_xbar_load_gating_prod, - .pg_gr_load_gating_prod = - gr_gm20b_pg_gr_load_gating_prod, - } -}; - -static int gm206_get_litter_value(struct gk20a *g, int value) -{ - int ret = -EINVAL; - - switch (value) { - case GPU_LIT_NUM_GPCS: - ret = proj_scal_litter_num_gpcs_v(); - break; - case GPU_LIT_NUM_PES_PER_GPC: - ret = proj_scal_litter_num_pes_per_gpc_v(); - break; - case GPU_LIT_NUM_ZCULL_BANKS: - ret = proj_scal_litter_num_zcull_banks_v(); - break; - case GPU_LIT_NUM_TPC_PER_GPC: - ret = proj_scal_litter_num_tpc_per_gpc_v(); - break; - case GPU_LIT_NUM_FBPS: - ret = proj_scal_litter_num_fbps_v(); - break; - case GPU_LIT_GPC_BASE: - ret = proj_gpc_base_v(); - break; - case GPU_LIT_GPC_STRIDE: - ret = proj_gpc_stride_v(); - break; - case GPU_LIT_GPC_SHARED_BASE: - ret = proj_gpc_shared_base_v(); - break; - case GPU_LIT_TPC_IN_GPC_BASE: - ret = proj_tpc_in_gpc_base_v(); - break; - case GPU_LIT_TPC_IN_GPC_STRIDE: - ret = proj_tpc_in_gpc_stride_v(); - break; - case GPU_LIT_TPC_IN_GPC_SHARED_BASE: - ret = proj_tpc_in_gpc_shared_base_v(); - break; - case GPU_LIT_PPC_IN_GPC_STRIDE: - ret = proj_ppc_in_gpc_stride_v(); - break; - case GPU_LIT_ROP_BASE: - ret = proj_rop_base_v(); - break; - case GPU_LIT_ROP_STRIDE: - ret = proj_rop_stride_v(); - break; - case GPU_LIT_ROP_SHARED_BASE: - ret = proj_rop_shared_base_v(); - break; - case GPU_LIT_HOST_NUM_ENGINES: - ret = proj_host_num_engines_v(); - break; - case GPU_LIT_HOST_NUM_PBDMA: - ret = proj_host_num_pbdma_v(); - break; - case GPU_LIT_LTC_STRIDE: - ret = proj_ltc_stride_v(); - break; - case GPU_LIT_LTS_STRIDE: - ret = proj_lts_stride_v(); - break; - case GPU_LIT_NUM_FBPAS: - ret = proj_scal_litter_num_fbpas_v(); - break; - case GPU_LIT_FBPA_STRIDE: - ret = proj_fbpa_stride_v(); - break; - default: - BUG(); - break; - } - - return ret; -} - -int gm206_init_hal(struct gk20a *g) -{ - struct gpu_ops *gops = &g->ops; - struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; - u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; - - *gops = gm206_ops; - - gops->privsecurity = 1; - gops->securegpccs = 1; - gops->pmupstate = false; - gm20b_init_mc(gops); - gm20b_init_ltc(gops); - gm206_init_gr(gops); - gm20b_init_ltc(gops); - gm20b_init_fb(gops); - g->ops.fb.set_use_full_comp_tag_line = NULL; - gm206_init_fifo(gops); - gm206_init_ce(gops); - gm20b_init_gr_ctx(gops); - gm206_init_mm(gops); - gm20b_init_clk_ops(gops); - gm20b_init_regops(gops); - gm20b_init_debug_ops(gops); - gk20a_init_dbg_session_ops(gops); - gm20b_init_cde_ops(gops); - gm20b_init_therm_ops(gops); - gk20a_init_tsg_ops(gops); -#if defined(CONFIG_GK20A_CYCLE_STATS) - gk20a_init_css_ops(gops); -#endif - gm206_init_bios_ops(gops); - switch(ver){ - case GK20A_GPUID_GM206: - gops->name = "gm206"; - break; - case GK20A_GPUID_GM204: - gops->name = "gm204"; - break; - default: - gk20a_err(g->dev, "no support for %x", ver); - BUG(); - } - gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics; - gops->get_litter_value = gm206_get_litter_value; - gops->gr_ctx.use_dma_for_fw_bootstrap = true; - - c->twod_class = FERMI_TWOD_A; - c->threed_class = MAXWELL_B; - c->compute_class = MAXWELL_COMPUTE_B; - c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A; - c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; - c->dma_copy_class = MAXWELL_DMA_COPY_A; - - return 0; -} diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.h b/drivers/gpu/nvgpu/gm206/hal_gm206.h deleted file mode 100644 index b7fab24c..00000000 --- a/drivers/gpu/nvgpu/gm206/hal_gm206.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _NVGPU_HAL_GM206_H -#define _NVGPU_HAL_GM206_H -struct gk20a; - -int gm206_init_hal(struct gk20a *gops); -#endif diff --git a/drivers/gpu/nvgpu/gm206/mm_gm206.c b/drivers/gpu/nvgpu/gm206/mm_gm206.c deleted file mode 100644 index 75c8a234..00000000 --- a/drivers/gpu/nvgpu/gm206/mm_gm206.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * GM206 memory management - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "gk20a/gk20a.h" -#include "gm20b/mm_gm20b.h" -#include "gm206/mm_gm206.h" - -#include -#include - -static size_t gm206_mm_get_vidmem_size(struct gk20a *g) -{ - u32 fbpas = top_num_fbpas_value_v( - gk20a_readl(g, top_num_fbpas_r())); - u32 ram = fbpa_cstatus_ramamount_v( - gk20a_readl(g, fbpa_cstatus_r())); - return (size_t)fbpas * ram * SZ_1M; -} - -void gm206_init_mm(struct gpu_ops *gops) -{ - gm20b_init_mm(gops); - gops->mm.get_vidmem_size = gm206_mm_get_vidmem_size; - gops->mm.get_physical_addr_bits = NULL; -} diff --git a/drivers/gpu/nvgpu/gm206/mm_gm206.h b/drivers/gpu/nvgpu/gm206/mm_gm206.h deleted file mode 100644 index 60aa6fe4..00000000 --- a/drivers/gpu/nvgpu/gm206/mm_gm206.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * GM206 memory management - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef MM_GM206_H -#define MM_GM206_H - -struct gpu_ops; - -void gm206_init_mm(struct gpu_ops *gops); - -#endif - -- cgit v1.2.2