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author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-06-02 08:08:37 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-06-04 18:21:35 -0400 |
commit | f99de40936236b4e8b00fa847f502c7b94af85c3 (patch) | |
tree | 0be307642c99a03e1807fbe5549e5c47fb6ded1e /drivers/gpu/nvgpu/gk20a | |
parent | 608101dbfa1c99069ca2abe9d70a204419f8e719 (diff) |
gpu: nvgpu: WPR & PMU interface update
Update WPR interface & PMU interface
to support latest ACR/PMU ucode versions
Change-Id: I4d1bd7a5c43751e96c1db58832cd316006d56954
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1158070
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 32 |
3 files changed, 35 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 85289087..3da19cc8 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -549,10 +549,10 @@ struct gpu_ops { | |||
549 | int (*falcon_clear_halt_interrupt_status)(struct gk20a *g, | 549 | int (*falcon_clear_halt_interrupt_status)(struct gk20a *g, |
550 | unsigned int timeout); | 550 | unsigned int timeout); |
551 | int (*init_falcon_setup_hw)(struct gk20a *g, | 551 | int (*init_falcon_setup_hw)(struct gk20a *g, |
552 | struct flcn_bl_dmem_desc *desc, u32 bl_sz); | 552 | void *desc, u32 bl_sz); |
553 | bool (*is_lazy_bootstrap)(u32 falcon_id); | 553 | bool (*is_lazy_bootstrap)(u32 falcon_id); |
554 | bool (*is_priv_load)(u32 falcon_id); | 554 | bool (*is_priv_load)(u32 falcon_id); |
555 | void (*get_wpr)(struct gk20a *g, u64 *base, u64 *size); | 555 | void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf); |
556 | int (*alloc_blob_space)(struct gk20a *g, | 556 | int (*alloc_blob_space)(struct gk20a *g, |
557 | size_t size, struct mem_desc *mem); | 557 | size_t size, struct mem_desc *mem); |
558 | int (*pmu_populate_loader_cfg)(struct gk20a *g, | 558 | int (*pmu_populate_loader_cfg)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 51ffc552..d12c5987 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -1623,7 +1623,7 @@ void pmu_copy_to_dmem(struct pmu_gk20a *pmu, | |||
1623 | return; | 1623 | return; |
1624 | } | 1624 | } |
1625 | 1625 | ||
1626 | static int pmu_idle(struct pmu_gk20a *pmu) | 1626 | int pmu_idle(struct pmu_gk20a *pmu) |
1627 | { | 1627 | { |
1628 | struct gk20a *g = gk20a_from_pmu(pmu); | 1628 | struct gk20a *g = gk20a_from_pmu(pmu); |
1629 | unsigned long end_jiffies = jiffies + | 1629 | unsigned long end_jiffies = jiffies + |
@@ -1714,7 +1714,7 @@ void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable) | |||
1714 | gk20a_dbg_fn("done"); | 1714 | gk20a_dbg_fn("done"); |
1715 | } | 1715 | } |
1716 | 1716 | ||
1717 | static int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | 1717 | int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) |
1718 | { | 1718 | { |
1719 | struct gk20a *g = gk20a_from_pmu(pmu); | 1719 | struct gk20a *g = gk20a_from_pmu(pmu); |
1720 | 1720 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index b8bb18a2..7d91b111 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -450,6 +450,31 @@ struct pmu_ucode_desc { | |||
450 | u32 compressed; | 450 | u32 compressed; |
451 | }; | 451 | }; |
452 | 452 | ||
453 | struct pmu_ucode_desc_v1 { | ||
454 | u32 descriptor_size; | ||
455 | u32 image_size; | ||
456 | u32 tools_version; | ||
457 | u32 app_version; | ||
458 | char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH]; | ||
459 | u32 bootloader_start_offset; | ||
460 | u32 bootloader_size; | ||
461 | u32 bootloader_imem_offset; | ||
462 | u32 bootloader_entry_point; | ||
463 | u32 app_start_offset; | ||
464 | u32 app_size; | ||
465 | u32 app_imem_offset; | ||
466 | u32 app_imem_entry; | ||
467 | u32 app_dmem_offset; | ||
468 | u32 app_resident_code_offset; | ||
469 | u32 app_resident_code_size; | ||
470 | u32 app_resident_data_offset; | ||
471 | u32 app_resident_data_size; | ||
472 | u32 nb_imem_overlays; | ||
473 | u32 nb_dmem_overlays; | ||
474 | struct {u32 start; u32 size; } load_ovl[64]; | ||
475 | u32 compressed; | ||
476 | }; | ||
477 | |||
453 | #define PMU_UNIT_REWIND (0x00) | 478 | #define PMU_UNIT_REWIND (0x00) |
454 | #define PMU_UNIT_PG (0x03) | 479 | #define PMU_UNIT_PG (0x03) |
455 | #define PMU_UNIT_INIT (0x07) | 480 | #define PMU_UNIT_INIT (0x07) |
@@ -1295,7 +1320,10 @@ struct pmu_pg_stats { | |||
1295 | 1320 | ||
1296 | struct pmu_gk20a { | 1321 | struct pmu_gk20a { |
1297 | 1322 | ||
1298 | struct pmu_ucode_desc *desc; | 1323 | union { |
1324 | struct pmu_ucode_desc *desc; | ||
1325 | struct pmu_ucode_desc_v1 *desc_v1; | ||
1326 | }; | ||
1299 | struct mem_desc ucode; | 1327 | struct mem_desc ucode; |
1300 | 1328 | ||
1301 | struct mem_desc pg_buf; | 1329 | struct mem_desc pg_buf; |
@@ -1427,5 +1455,7 @@ void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, | |||
1427 | void gk20a_pmu_elpg_statistics(struct gk20a *g, | 1455 | void gk20a_pmu_elpg_statistics(struct gk20a *g, |
1428 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); | 1456 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); |
1429 | int gk20a_pmu_reset(struct gk20a *g); | 1457 | int gk20a_pmu_reset(struct gk20a *g); |
1458 | int pmu_idle(struct pmu_gk20a *pmu); | ||
1459 | int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable); | ||
1430 | 1460 | ||
1431 | #endif /*__PMU_GK20A_H__*/ | 1461 | #endif /*__PMU_GK20A_H__*/ |