From f99de40936236b4e8b00fa847f502c7b94af85c3 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 2 Jun 2016 17:38:37 +0530 Subject: gpu: nvgpu: WPR & PMU interface update Update WPR interface & PMU interface to support latest ACR/PMU ucode versions Change-Id: I4d1bd7a5c43751e96c1db58832cd316006d56954 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1158070 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/gk20a.h | 4 ++-- drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 4 ++-- drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 32 +++++++++++++++++++++++++++++++- 3 files changed, 35 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 85289087..3da19cc8 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -549,10 +549,10 @@ struct gpu_ops { int (*falcon_clear_halt_interrupt_status)(struct gk20a *g, unsigned int timeout); int (*init_falcon_setup_hw)(struct gk20a *g, - struct flcn_bl_dmem_desc *desc, u32 bl_sz); + void *desc, u32 bl_sz); bool (*is_lazy_bootstrap)(u32 falcon_id); bool (*is_priv_load)(u32 falcon_id); - void (*get_wpr)(struct gk20a *g, u64 *base, u64 *size); + void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf); int (*alloc_blob_space)(struct gk20a *g, size_t size, struct mem_desc *mem); int (*pmu_populate_loader_cfg)(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 51ffc552..d12c5987 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -1623,7 +1623,7 @@ void pmu_copy_to_dmem(struct pmu_gk20a *pmu, return; } -static int pmu_idle(struct pmu_gk20a *pmu) +int pmu_idle(struct pmu_gk20a *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); unsigned long end_jiffies = jiffies + @@ -1714,7 +1714,7 @@ void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable) gk20a_dbg_fn("done"); } -static int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) +int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) { struct gk20a *g = gk20a_from_pmu(pmu); diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index b8bb18a2..7d91b111 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h @@ -450,6 +450,31 @@ struct pmu_ucode_desc { u32 compressed; }; +struct pmu_ucode_desc_v1 { + u32 descriptor_size; + u32 image_size; + u32 tools_version; + u32 app_version; + char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH]; + u32 bootloader_start_offset; + u32 bootloader_size; + u32 bootloader_imem_offset; + u32 bootloader_entry_point; + u32 app_start_offset; + u32 app_size; + u32 app_imem_offset; + u32 app_imem_entry; + u32 app_dmem_offset; + u32 app_resident_code_offset; + u32 app_resident_code_size; + u32 app_resident_data_offset; + u32 app_resident_data_size; + u32 nb_imem_overlays; + u32 nb_dmem_overlays; + struct {u32 start; u32 size; } load_ovl[64]; + u32 compressed; +}; + #define PMU_UNIT_REWIND (0x00) #define PMU_UNIT_PG (0x03) #define PMU_UNIT_INIT (0x07) @@ -1295,7 +1320,10 @@ struct pmu_pg_stats { struct pmu_gk20a { - struct pmu_ucode_desc *desc; + union { + struct pmu_ucode_desc *desc; + struct pmu_ucode_desc_v1 *desc_v1; + }; struct mem_desc ucode; struct mem_desc pg_buf; @@ -1427,5 +1455,7 @@ void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); int gk20a_pmu_reset(struct gk20a *g); +int pmu_idle(struct pmu_gk20a *pmu); +int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable); #endif /*__PMU_GK20A_H__*/ -- cgit v1.2.2