diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2017-04-19 19:47:13 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-24 07:55:36 -0400 |
commit | b03afb6d5c4bbca5a26cc95027491c816e5e1f6d (patch) | |
tree | b59ae1b881877cf52ca921a5bf9d884f78fac648 /drivers/gpu/nvgpu/gk20a | |
parent | a823c72219d3bb96bc9489e84b64e0038e7119d7 (diff) |
gpu: nvgpu: add ioctls to get current timeslice
Add the following ioctls
- NVGPU_CHANNEL_IOCTL_GET_TIMESLICE for channel timeslice in us
- NVGPU_TSG_IOCTL_GET_TIMESLICE for TSG timeslice in us
If timeslice has not been set explicitly, ioctl returns the
default timeslice that will be used when programming the runlist
entry.
Bug 1883271
Change-Id: Ib18fdd836323b1a2d4efceb1e27d07713bd6fca5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1469040
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | 1 |
7 files changed, 40 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 9e3bc05e..6cb77d67 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -146,6 +146,16 @@ int channel_gk20a_commit_va(struct channel_gk20a *c) | |||
146 | return 0; | 146 | return 0; |
147 | } | 147 | } |
148 | 148 | ||
149 | u32 gk20a_channel_get_timeslice(struct channel_gk20a *ch) | ||
150 | { | ||
151 | struct gk20a *g = ch->g; | ||
152 | |||
153 | if (!ch->timeslice_us) | ||
154 | return g->ops.fifo.default_timeslice_us(g); | ||
155 | |||
156 | return ch->timeslice_us; | ||
157 | } | ||
158 | |||
149 | int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, | 159 | int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, |
150 | int timeslice_period, | 160 | int timeslice_period, |
151 | int *__timeslice_timeout, int *__timeslice_scale) | 161 | int *__timeslice_timeout, int *__timeslice_scale) |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index bbc1a72a..d3ab9b27 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -388,6 +388,7 @@ void channel_gk20a_joblist_lock(struct channel_gk20a *c); | |||
388 | void channel_gk20a_joblist_unlock(struct channel_gk20a *c); | 388 | void channel_gk20a_joblist_unlock(struct channel_gk20a *c); |
389 | bool channel_gk20a_joblist_is_empty(struct channel_gk20a *c); | 389 | bool channel_gk20a_joblist_is_empty(struct channel_gk20a *c); |
390 | 390 | ||
391 | u32 gk20a_channel_get_timeslice(struct channel_gk20a *ch); | ||
391 | int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, | 392 | int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, |
392 | int timeslice_period, | 393 | int timeslice_period, |
393 | int *__timeslice_timeout, int *__timeslice_scale); | 394 | int *__timeslice_timeout, int *__timeslice_scale); |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 8085318d..f536b374 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2920,14 +2920,24 @@ void gk20a_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) | |||
2920 | ram_rl_entry_timeslice_timeout_f(tsg->timeslice_timeout); | 2920 | ram_rl_entry_timeslice_timeout_f(tsg->timeslice_timeout); |
2921 | else | 2921 | else |
2922 | runlist_entry_0 |= | 2922 | runlist_entry_0 |= |
2923 | ram_rl_entry_timeslice_scale_3_f() | | 2923 | ram_rl_entry_timeslice_scale_f( |
2924 | ram_rl_entry_timeslice_timeout_128_f(); | 2924 | NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE) | |
2925 | ram_rl_entry_timeslice_timeout_f( | ||
2926 | NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT); | ||
2925 | 2927 | ||
2926 | runlist[0] = runlist_entry_0; | 2928 | runlist[0] = runlist_entry_0; |
2927 | runlist[1] = 0; | 2929 | runlist[1] = 0; |
2928 | 2930 | ||
2929 | } | 2931 | } |
2930 | 2932 | ||
2933 | u32 gk20a_fifo_default_timeslice_us(struct gk20a *g) | ||
2934 | { | ||
2935 | return (((u64)(NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT << | ||
2936 | NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE) * | ||
2937 | (u64)g->ptimer_src_freq) / | ||
2938 | (u64)PTIMER_REF_FREQ_HZ); | ||
2939 | } | ||
2940 | |||
2931 | void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist) | 2941 | void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist) |
2932 | { | 2942 | { |
2933 | runlist[0] = ram_rl_entry_chid_f(ch->hw_chid); | 2943 | runlist[0] = ram_rl_entry_chid_f(ch->hw_chid); |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 0bec9e82..b09fde65 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -47,6 +47,9 @@ | |||
47 | #define RC_TYPE_PBDMA_FAULT 2 | 47 | #define RC_TYPE_PBDMA_FAULT 2 |
48 | #define RC_TYPE_NO_RC 0xff | 48 | #define RC_TYPE_NO_RC 0xff |
49 | 49 | ||
50 | #define NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT 128UL | ||
51 | #define NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE 3UL | ||
52 | |||
50 | /* | 53 | /* |
51 | * Number of entries in the kickoff latency buffer, used to calculate | 54 | * Number of entries in the kickoff latency buffer, used to calculate |
52 | * the profiling and histogram. This number is calculated to be statistically | 55 | * the profiling and histogram. This number is calculated to be statistically |
@@ -399,4 +402,6 @@ void gk20a_fifo_reset_pbdma_method(struct gk20a *g, int pbdma_id, | |||
399 | int pbdma_method_index); | 402 | int pbdma_method_index); |
400 | unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, | 403 | unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, |
401 | u32 pbdma_intr_0, u32 *handled, u32 *error_notifier); | 404 | u32 pbdma_intr_0, u32 *handled, u32 *error_notifier); |
405 | |||
406 | u32 gk20a_fifo_default_timeslice_us(struct gk20a *g); | ||
402 | #endif /*__GR_GK20A_H__*/ | 407 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 9ab0d202..b3292ac4 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -445,6 +445,7 @@ struct gpu_ops { | |||
445 | int (*channel_set_timeslice)(struct channel_gk20a *ch, | 445 | int (*channel_set_timeslice)(struct channel_gk20a *ch, |
446 | u32 timeslice); | 446 | u32 timeslice); |
447 | int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice); | 447 | int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice); |
448 | u32 (*default_timeslice_us)(struct gk20a *); | ||
448 | int (*force_reset_ch)(struct channel_gk20a *ch, | 449 | int (*force_reset_ch)(struct channel_gk20a *ch, |
449 | u32 err_code, bool verbose); | 450 | u32 err_code, bool verbose); |
450 | int (*engine_enum_from_type)(struct gk20a *g, u32 engine_type, | 451 | int (*engine_enum_from_type)(struct gk20a *g, u32 engine_type, |
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index f9884cfb..9cb5b262 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -211,6 +211,16 @@ int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) | |||
211 | return g->ops.fifo.tsg_set_timeslice(tsg, timeslice); | 211 | return g->ops.fifo.tsg_set_timeslice(tsg, timeslice); |
212 | } | 212 | } |
213 | 213 | ||
214 | u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg) | ||
215 | { | ||
216 | struct gk20a *g = tsg->g; | ||
217 | |||
218 | if (!tsg->timeslice_us) | ||
219 | return g->ops.fifo.default_timeslice_us(g); | ||
220 | |||
221 | return tsg->timeslice_us; | ||
222 | } | ||
223 | |||
214 | static void release_used_tsg(struct fifo_gk20a *f, struct tsg_gk20a *tsg) | 224 | static void release_used_tsg(struct fifo_gk20a *f, struct tsg_gk20a *tsg) |
215 | { | 225 | { |
216 | nvgpu_mutex_acquire(&f->tsg_inuse_mutex); | 226 | nvgpu_mutex_acquire(&f->tsg_inuse_mutex); |
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h index 945058a2..5a13c912 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | |||
@@ -70,6 +70,7 @@ void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg, | |||
70 | int event_id); | 70 | int event_id); |
71 | int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level); | 71 | int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level); |
72 | int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); | 72 | int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); |
73 | u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg); | ||
73 | int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg, | 74 | int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg, |
74 | u32 priority); | 75 | u32 priority); |
75 | 76 | ||