From b03afb6d5c4bbca5a26cc95027491c816e5e1f6d Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Wed, 19 Apr 2017 16:47:13 -0700 Subject: gpu: nvgpu: add ioctls to get current timeslice Add the following ioctls - NVGPU_CHANNEL_IOCTL_GET_TIMESLICE for channel timeslice in us - NVGPU_TSG_IOCTL_GET_TIMESLICE for TSG timeslice in us If timeslice has not been set explicitly, ioctl returns the default timeslice that will be used when programming the runlist entry. Bug 1883271 Change-Id: Ib18fdd836323b1a2d4efceb1e27d07713bd6fca5 Signed-off-by: Thomas Fleury Reviewed-on: http://git-master/r/1469040 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 10 ++++++++++ drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 14 ++++++++++++-- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 5 +++++ drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 10 ++++++++++ drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | 1 + 7 files changed, 40 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a') diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 9e3bc05e..6cb77d67 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c @@ -146,6 +146,16 @@ int channel_gk20a_commit_va(struct channel_gk20a *c) return 0; } +u32 gk20a_channel_get_timeslice(struct channel_gk20a *ch) +{ + struct gk20a *g = ch->g; + + if (!ch->timeslice_us) + return g->ops.fifo.default_timeslice_us(g); + + return ch->timeslice_us; +} + int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, int timeslice_period, int *__timeslice_timeout, int *__timeslice_scale) diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index bbc1a72a..d3ab9b27 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h @@ -388,6 +388,7 @@ void channel_gk20a_joblist_lock(struct channel_gk20a *c); void channel_gk20a_joblist_unlock(struct channel_gk20a *c); bool channel_gk20a_joblist_is_empty(struct channel_gk20a *c); +u32 gk20a_channel_get_timeslice(struct channel_gk20a *ch); int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, int timeslice_period, int *__timeslice_timeout, int *__timeslice_scale); diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 8085318d..f536b374 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -2920,14 +2920,24 @@ void gk20a_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) ram_rl_entry_timeslice_timeout_f(tsg->timeslice_timeout); else runlist_entry_0 |= - ram_rl_entry_timeslice_scale_3_f() | - ram_rl_entry_timeslice_timeout_128_f(); + ram_rl_entry_timeslice_scale_f( + NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE) | + ram_rl_entry_timeslice_timeout_f( + NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT); runlist[0] = runlist_entry_0; runlist[1] = 0; } +u32 gk20a_fifo_default_timeslice_us(struct gk20a *g) +{ + return (((u64)(NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT << + NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE) * + (u64)g->ptimer_src_freq) / + (u64)PTIMER_REF_FREQ_HZ); +} + void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist) { runlist[0] = ram_rl_entry_chid_f(ch->hw_chid); diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 0bec9e82..b09fde65 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -47,6 +47,9 @@ #define RC_TYPE_PBDMA_FAULT 2 #define RC_TYPE_NO_RC 0xff +#define NVGPU_FIFO_DEFAULT_TIMESLICE_TIMEOUT 128UL +#define NVGPU_FIFO_DEFAULT_TIMESLICE_SCALE 3UL + /* * Number of entries in the kickoff latency buffer, used to calculate * the profiling and histogram. This number is calculated to be statistically @@ -399,4 +402,6 @@ void gk20a_fifo_reset_pbdma_method(struct gk20a *g, int pbdma_id, int pbdma_method_index); unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0, u32 *handled, u32 *error_notifier); + +u32 gk20a_fifo_default_timeslice_us(struct gk20a *g); #endif /*__GR_GK20A_H__*/ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 9ab0d202..b3292ac4 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -445,6 +445,7 @@ struct gpu_ops { int (*channel_set_timeslice)(struct channel_gk20a *ch, u32 timeslice); int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice); + u32 (*default_timeslice_us)(struct gk20a *); int (*force_reset_ch)(struct channel_gk20a *ch, u32 err_code, bool verbose); int (*engine_enum_from_type)(struct gk20a *g, u32 engine_type, diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index f9884cfb..9cb5b262 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c @@ -211,6 +211,16 @@ int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) return g->ops.fifo.tsg_set_timeslice(tsg, timeslice); } +u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg) +{ + struct gk20a *g = tsg->g; + + if (!tsg->timeslice_us) + return g->ops.fifo.default_timeslice_us(g); + + return tsg->timeslice_us; +} + static void release_used_tsg(struct fifo_gk20a *f, struct tsg_gk20a *tsg) { nvgpu_mutex_acquire(&f->tsg_inuse_mutex); diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h index 945058a2..5a13c912 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h @@ -70,6 +70,7 @@ void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg, int event_id); int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level); int gk20a_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); +u32 gk20a_tsg_get_timeslice(struct tsg_gk20a *tsg); int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg, u32 priority); -- cgit v1.2.2