diff options
author | Rajkumar Kasirajan <rkasirajan@nvidia.com> | 2017-03-09 10:52:50 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-14 14:47:05 -0400 |
commit | e4a131a98d47740098c554425c532a2e3e48274d (patch) | |
tree | b385ca83be591e6dce7c009b65b06c3403c0c65a /drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |
parent | bf717d6273fa2d618dd2adf9bc349881f599e102 (diff) |
Revert "gpu: nvgpu: change stall intr handling order"
This reverts commit 35f0cf0efefe4a64ee25a5b118338b15e552dcb0 as
it caused lp0 suspend/resume failure.
Bug 1886110
Change-Id: Ib62207650344180361b6529f716f77b84528cd56
Signed-off-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-on: http://git-master/r/1317986
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index 90bd95ac..a44df1e8 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -76,6 +76,8 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
76 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | 76 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); |
77 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 77 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); |
78 | 78 | ||
79 | if (platform->is_fmodel) | ||
80 | return; | ||
79 | 81 | ||
80 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); | 82 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); |
81 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); | 83 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); |
@@ -88,6 +90,7 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
88 | pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) { | 90 | pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) { |
89 | gk20a_reset_priv_ring(g); | 91 | gk20a_reset_priv_ring(g); |
90 | } | 92 | } |
93 | |||
91 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { | 94 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { |
92 | gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", | 95 | gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", |
93 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), | 96 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), |
@@ -106,9 +109,6 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
106 | } | 109 | } |
107 | } | 110 | } |
108 | 111 | ||
109 | if (platform->is_fmodel) | ||
110 | return; | ||
111 | |||
112 | cmd = gk20a_readl(g, pri_ringmaster_command_r()); | 112 | cmd = gk20a_readl(g, pri_ringmaster_command_r()); |
113 | cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), | 113 | cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), |
114 | pri_ringmaster_command_cmd_ack_interrupt_f()); | 114 | pri_ringmaster_command_cmd_ack_interrupt_f()); |