diff options
| author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-08-25 18:39:14 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-28 10:54:47 -0400 |
| commit | 69d7652aaa9cf94873cccae13c7b6f6a4eb224af (patch) | |
| tree | 8ec8f2c7f26ac0b324742d9d6c8436235fb1a6ce /drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |
| parent | c3817a56b7ea79cb68bd26414df07363ebf15b3e (diff) | |
gpu: nvgpu: Dump error on priv ring intr
Write an error to UART on priv ring error. This uncovers any
accesses to missing registers or illegal accesses to registers.
Bug 1846641
Change-Id: Ic1e5ecadcd95777f2b3f7bd77accf98ddce97282
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1294683
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c')
| -rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index 1584ffda..239d8efd 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
| @@ -80,7 +80,7 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
| 80 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); | 80 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); |
| 81 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); | 81 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); |
| 82 | 82 | ||
| 83 | gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x," | 83 | nvgpu_err(g, "ringmaster intr status0: 0x%08x," |
| 84 | "status1: 0x%08x", status0, status1); | 84 | "status1: 0x%08x", status0, status1); |
| 85 | 85 | ||
| 86 | if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0 || | 86 | if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0 || |
| @@ -90,7 +90,7 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
| 90 | } | 90 | } |
| 91 | 91 | ||
| 92 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { | 92 | if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { |
| 93 | gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", | 93 | nvgpu_err(g, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", |
| 94 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), | 94 | gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), |
| 95 | gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), | 95 | gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), |
| 96 | gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()), | 96 | gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()), |
| @@ -99,7 +99,7 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
| 99 | 99 | ||
| 100 | for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { | 100 | for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { |
| 101 | if (status1 & BIT(gpc)) { | 101 | if (status1 & BIT(gpc)) { |
| 102 | gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, | 102 | nvgpu_err(g, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, |
| 103 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride), | 103 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride), |
| 104 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride), | 104 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride), |
| 105 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride), | 105 | gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride), |