gpu: nvgpu: Falcon-controller interface update

Moved falcon-controller common interface code
from pmu_common.h to flcnif_cmn.h file.
Interfaces are common for falcons irrespective
of F/W on falcon controllers

Jira NVGPU-19

Change-Id: Iad11b2fade8cf6716888773b2b1c23919cbcc07b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1296695
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 16 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index 84377d0b..dc23005e 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -23,7 +23,7 @@
 
 #include <linux/version.h>
 #include "pmu_api.h"
-#include "pmu_common.h"
+#include <nvgpu/flcnif_cmn.h>
 #include "pmuif/nvgpu_gpmu_cmdif.h"
 
 /* defined by pmu hw spec */
@@ -124,21 +124,6 @@ struct pmu_ucode_desc_v1 {
         u32 compressed;
 };
 
-#define PMU_DMEM_ALLOC_ALIGNMENT        (4)
-#define PMU_DMEM_ALIGNMENT              (4)
-
-#define PMU_CMD_FLAGS_PMU_MASK          (0xF0)
-
-#define PMU_CMD_FLAGS_STATUS            BIT(0)
-#define PMU_CMD_FLAGS_INTR              BIT(1)
-#define PMU_CMD_FLAGS_EVENT             BIT(2)
-#define PMU_CMD_FLAGS_WATERMARK         BIT(3)
-
-#define PMU_MSG_HDR_SIZE        sizeof(struct pmu_hdr)
-#define PMU_CMD_HDR_SIZE        sizeof(struct pmu_hdr)
-
-
-
 /***************************** ACR ERROR CODES  ******************************/
 /*!
  * Error codes used in PMU-ACR Task