diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-06-02 15:25:57 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-06-05 23:44:19 -0400 |
commit | 1d2e66540a37f04add5694d7aee9350cf6f6a78d (patch) | |
tree | 58b8d1ab7c0e7d2e51050113877bbc51d0c6ff39 /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |
parent | b77cca1d62790176442df8b9bb7f82b05a0c190f (diff) |
gpu: nvgpu: Fix calculation of timeout
Fix calculation of timeout in multiple places. The #defines
GR_IDLE_CHECK_DEFAULT and GR_IDLE_CHECK_MAX are meant to be used
only for defining the frequency of checking for timeout. Using them
for actual timeouts makes the timeout really short.
Change-Id: I3d0f8cbc91d619be8e5a9168ee1ab1d6298f129b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1158269
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index b60d1b71..8ce7f32d 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -37,6 +37,9 @@ | |||
37 | 37 | ||
38 | #define GK20A_PMU_UCODE_IMAGE "gpmu_ucode.bin" | 38 | #define GK20A_PMU_UCODE_IMAGE "gpmu_ucode.bin" |
39 | 39 | ||
40 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 | ||
41 | #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 | ||
42 | |||
40 | #define gk20a_dbg_pmu(fmt, arg...) \ | 43 | #define gk20a_dbg_pmu(fmt, arg...) \ |
41 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 44 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) |
42 | 45 | ||
@@ -2119,7 +2122,8 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2119 | gk20a_dbg_fn(""); | 2122 | gk20a_dbg_fn(""); |
2120 | 2123 | ||
2121 | if (enable) { | 2124 | if (enable) { |
2122 | int retries = GR_IDLE_CHECK_MAX / GR_IDLE_CHECK_DEFAULT; | 2125 | int retries = PMU_MEM_SCRUBBING_TIMEOUT_MAX / |
2126 | PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT; | ||
2123 | gk20a_enable(g, mc_enable_pwr_enabled_f()); | 2127 | gk20a_enable(g, mc_enable_pwr_enabled_f()); |
2124 | 2128 | ||
2125 | if (g->ops.clock_gating.slcg_pmu_load_gating_prod) | 2129 | if (g->ops.clock_gating.slcg_pmu_load_gating_prod) |
@@ -2138,7 +2142,7 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2138 | gk20a_dbg_fn("done"); | 2142 | gk20a_dbg_fn("done"); |
2139 | return 0; | 2143 | return 0; |
2140 | } | 2144 | } |
2141 | udelay(GR_IDLE_CHECK_DEFAULT); | 2145 | udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT); |
2142 | } while (--retries || !tegra_platform_is_silicon()); | 2146 | } while (--retries || !tegra_platform_is_silicon()); |
2143 | 2147 | ||
2144 | gk20a_disable(g, mc_enable_pwr_enabled_f()); | 2148 | gk20a_disable(g, mc_enable_pwr_enabled_f()); |