diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-03-29 18:00:24 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-11 13:56:06 -0400 |
commit | 19fdb429c2b04d13faecad8b2e5466e9f3c7b8c7 (patch) | |
tree | e92f6d93ae2593286546f983b9a1fff8638aa9a6 /drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |
parent | 1a4647272f4fe50137c79583b698c1ef6f5def12 (diff) |
gpu: nvgpu: Wrappers for checking platform type
Add nvgpu_* wrappers for determining if we're running in simulation
or silicon, and if we're running in hypervisor.
The new wrappers require struct gk20a pointer, and gk20a_fence_wait()
did not have access to one. Add struct gk20a pointer as the first
parameter.
JIRA NVGPU-16
Change-Id: I73b2b8f091ca29fb1827054abd2adaf583710331
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1331565
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/pmu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 17 |
1 files changed, 4 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 38b8da9c..7df0c71c 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -3642,19 +3642,10 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) | |||
3642 | 3642 | ||
3643 | gk20a_dbg_fn(""); | 3643 | gk20a_dbg_fn(""); |
3644 | 3644 | ||
3645 | if (tegra_cpu_is_asim()) { | 3645 | gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id), |
3646 | /* TBD: calculate threshold for silicon */ | 3646 | PMU_PG_IDLE_THRESHOLD); |
3647 | gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id), | 3647 | gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id), |
3648 | PMU_PG_IDLE_THRESHOLD_SIM); | 3648 | PMU_PG_POST_POWERUP_IDLE_THRESHOLD); |
3649 | gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id), | ||
3650 | PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM); | ||
3651 | } else { | ||
3652 | /* TBD: calculate threshold for silicon */ | ||
3653 | gk20a_writel(g, pwr_pmu_pg_idlefilth_r(pg_engine_id), | ||
3654 | PMU_PG_IDLE_THRESHOLD); | ||
3655 | gk20a_writel(g, pwr_pmu_pg_ppuidlefilth_r(pg_engine_id), | ||
3656 | PMU_PG_POST_POWERUP_IDLE_THRESHOLD); | ||
3657 | } | ||
3658 | 3649 | ||
3659 | if (g->ops.pmu.pmu_pg_init_param) | 3650 | if (g->ops.pmu.pmu_pg_init_param) |
3660 | g->ops.pmu.pmu_pg_init_param(g, pg_engine_id); | 3651 | g->ops.pmu.pmu_pg_init_param(g, pg_engine_id); |