diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-05 21:01:12 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-09 14:57:47 -0400 |
commit | f14152c081d94710dbde843b8dcd9b3981afb831 (patch) | |
tree | 6ebbe3f66ba866d3ef1af6728199a3db597e3575 /drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |
parent | df05d2a7c214bc8cdb887f1609853d0f424ef6f1 (diff) |
gpu: nvgpu: Support 3 PEs per GPC
Old code maxed at 2 PEs per GPC. Support 3 PEs and add code to make
sure we will get a warning if hardware supports more than that.
JIRA DNVGPU-6
Change-Id: Id6061567bad20474f4b4a7a0959be3426e5e4828
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1142440
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index e1e6e262..24123eea 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -36,6 +36,8 @@ | |||
36 | #define GK20A_FECS_UCODE_IMAGE "fecs.bin" | 36 | #define GK20A_FECS_UCODE_IMAGE "fecs.bin" |
37 | #define GK20A_GPCCS_UCODE_IMAGE "gpccs.bin" | 37 | #define GK20A_GPCCS_UCODE_IMAGE "gpccs.bin" |
38 | 38 | ||
39 | #define GK20A_GR_MAX_PES_PER_GPC 3 | ||
40 | |||
39 | enum /* global_ctx_buffer */ { | 41 | enum /* global_ctx_buffer */ { |
40 | CIRCULAR = 0, | 42 | CIRCULAR = 0, |
41 | PAGEPOOL = 1, | 43 | PAGEPOOL = 1, |
@@ -270,8 +272,8 @@ struct gr_gk20a { | |||
270 | u32 *gpc_tpc_mask; | 272 | u32 *gpc_tpc_mask; |
271 | u32 zcb_count; | 273 | u32 zcb_count; |
272 | u32 *gpc_zcb_count; | 274 | u32 *gpc_zcb_count; |
273 | u32 *pes_tpc_count[2]; | 275 | u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC]; |
274 | u32 *pes_tpc_mask[2]; | 276 | u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC]; |
275 | u32 *gpc_skip_mask; | 277 | u32 *gpc_skip_mask; |
276 | 278 | ||
277 | u32 bundle_cb_default_size; | 279 | u32 bundle_cb_default_size; |