From f14152c081d94710dbde843b8dcd9b3981afb831 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 5 May 2016 18:01:12 -0700 Subject: gpu: nvgpu: Support 3 PEs per GPC Old code maxed at 2 PEs per GPC. Support 3 PEs and add code to make sure we will get a warning if hardware supports more than that. JIRA DNVGPU-6 Change-Id: Id6061567bad20474f4b4a7a0959be3426e5e4828 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1142440 --- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index e1e6e262..24123eea 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -36,6 +36,8 @@ #define GK20A_FECS_UCODE_IMAGE "fecs.bin" #define GK20A_GPCCS_UCODE_IMAGE "gpccs.bin" +#define GK20A_GR_MAX_PES_PER_GPC 3 + enum /* global_ctx_buffer */ { CIRCULAR = 0, PAGEPOOL = 1, @@ -270,8 +272,8 @@ struct gr_gk20a { u32 *gpc_tpc_mask; u32 zcb_count; u32 *gpc_zcb_count; - u32 *pes_tpc_count[2]; - u32 *pes_tpc_mask[2]; + u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC]; + u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC]; u32 *gpc_skip_mask; u32 bundle_cb_default_size; -- cgit v1.2.2