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authorAlex Waterman <alexw@nvidia.com>2018-03-06 13:43:16 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-07 21:04:41 -0500
commit418f31cd91a5c3ca45f0920ed64205def49c8a80 (patch)
tree17e3e04065679788aeeff645842866df0d59ccd0 /drivers/gpu/nvgpu/gk20a/gr_gk20a.c
parentf85a0d3e00b53453f3d5ca556f15465078473f31 (diff)
gpu: nvgpu: Enable IO coherency on GV100
This reverts commit 848af2ce6de6140323a6ffe3075bf8021e119434. This is a revert of a revert, etc, etc. It re-enables IO coherence again. JIRA EVLR-2333 Change-Id: Ibf97dce2f892e48a1200a06cd38a1c5d9603be04 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1669722 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c33
1 files changed, 19 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 8b07619d..61975106 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -742,13 +742,14 @@ void gr_gk20a_ctx_patch_write(struct gk20a *g,
742 742
743static u32 fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block) 743static u32 fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block)
744{ 744{
745 u32 ptr = u64_lo32(nvgpu_inst_block_addr(g, inst_block) 745 u64 ptr = nvgpu_inst_block_addr(g, inst_block) >>
746 >> ram_in_base_shift_v()); 746 ram_in_base_shift_v();
747 u32 aperture = nvgpu_aperture_mask(g, inst_block, 747 u32 aperture = nvgpu_aperture_mask(g, inst_block,
748 gr_fecs_current_ctx_target_sys_mem_ncoh_f(), 748 gr_fecs_current_ctx_target_sys_mem_ncoh_f(),
749 gr_fecs_current_ctx_target_vid_mem_f()); 749 gr_fecs_current_ctx_target_sys_mem_coh_f(),
750 gr_fecs_current_ctx_target_vid_mem_f());
750 751
751 return gr_fecs_current_ctx_ptr_f(ptr) | aperture | 752 return gr_fecs_current_ctx_ptr_f(u64_lo32(ptr)) | aperture |
752 gr_fecs_current_ctx_valid_f(1); 753 gr_fecs_current_ctx_valid_f(1);
753} 754}
754 755
@@ -2199,16 +2200,18 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g)
2199 2200
2200 inst_ptr = nvgpu_inst_block_addr(g, &ucode_info->inst_blk_desc); 2201 inst_ptr = nvgpu_inst_block_addr(g, &ucode_info->inst_blk_desc);
2201 gk20a_writel(g, gr_fecs_new_ctx_r(), 2202 gk20a_writel(g, gr_fecs_new_ctx_r(),
2202 gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) | 2203 gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) |
2203 nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, 2204 nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc,
2204 gr_fecs_new_ctx_target_sys_mem_ncoh_f(), 2205 gr_fecs_new_ctx_target_sys_mem_ncoh_f(),
2206 gr_fecs_new_ctx_target_sys_mem_coh_f(),
2205 gr_fecs_new_ctx_target_vid_mem_f()) | 2207 gr_fecs_new_ctx_target_vid_mem_f()) |
2206 gr_fecs_new_ctx_valid_m()); 2208 gr_fecs_new_ctx_valid_m());
2207 2209
2208 gk20a_writel(g, gr_fecs_arb_ctx_ptr_r(), 2210 gk20a_writel(g, gr_fecs_arb_ctx_ptr_r(),
2209 gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) | 2211 gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) |
2210 nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, 2212 nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc,
2211 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(), 2213 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(),
2214 gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(),
2212 gr_fecs_arb_ctx_ptr_target_vid_mem_f())); 2215 gr_fecs_arb_ctx_ptr_target_vid_mem_f()));
2213 2216
2214 gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7); 2217 gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7);
@@ -4440,8 +4443,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4440 4443
4441 gk20a_writel(g, fb_mmu_debug_wr_r(), 4444 gk20a_writel(g, fb_mmu_debug_wr_r(),
4442 nvgpu_aperture_mask(g, &gr->mmu_wr_mem, 4445 nvgpu_aperture_mask(g, &gr->mmu_wr_mem,
4443 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), 4446 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
4444 fb_mmu_debug_wr_aperture_vid_mem_f()) | 4447 fb_mmu_debug_wr_aperture_sys_mem_coh_f(),
4448 fb_mmu_debug_wr_aperture_vid_mem_f()) |
4445 fb_mmu_debug_wr_vol_false_f() | 4449 fb_mmu_debug_wr_vol_false_f() |
4446 fb_mmu_debug_wr_addr_f(addr)); 4450 fb_mmu_debug_wr_addr_f(addr));
4447 4451
@@ -4450,8 +4454,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
4450 4454
4451 gk20a_writel(g, fb_mmu_debug_rd_r(), 4455 gk20a_writel(g, fb_mmu_debug_rd_r(),
4452 nvgpu_aperture_mask(g, &gr->mmu_rd_mem, 4456 nvgpu_aperture_mask(g, &gr->mmu_rd_mem,
4453 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), 4457 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(),
4454 fb_mmu_debug_rd_aperture_vid_mem_f()) | 4458 fb_mmu_debug_wr_aperture_sys_mem_coh_f(),
4459 fb_mmu_debug_rd_aperture_vid_mem_f()) |
4455 fb_mmu_debug_rd_vol_false_f() | 4460 fb_mmu_debug_rd_vol_false_f() |
4456 fb_mmu_debug_rd_addr_f(addr)); 4461 fb_mmu_debug_rd_addr_f(addr));
4457 4462