From 418f31cd91a5c3ca45f0920ed64205def49c8a80 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 6 Mar 2018 10:43:16 -0800 Subject: gpu: nvgpu: Enable IO coherency on GV100 This reverts commit 848af2ce6de6140323a6ffe3075bf8021e119434. This is a revert of a revert, etc, etc. It re-enables IO coherence again. JIRA EVLR-2333 Change-Id: Ibf97dce2f892e48a1200a06cd38a1c5d9603be04 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1669722 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gr_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 8b07619d..61975106 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -742,13 +742,14 @@ void gr_gk20a_ctx_patch_write(struct gk20a *g, static u32 fecs_current_ctx_data(struct gk20a *g, struct nvgpu_mem *inst_block) { - u32 ptr = u64_lo32(nvgpu_inst_block_addr(g, inst_block) - >> ram_in_base_shift_v()); + u64 ptr = nvgpu_inst_block_addr(g, inst_block) >> + ram_in_base_shift_v(); u32 aperture = nvgpu_aperture_mask(g, inst_block, - gr_fecs_current_ctx_target_sys_mem_ncoh_f(), - gr_fecs_current_ctx_target_vid_mem_f()); + gr_fecs_current_ctx_target_sys_mem_ncoh_f(), + gr_fecs_current_ctx_target_sys_mem_coh_f(), + gr_fecs_current_ctx_target_vid_mem_f()); - return gr_fecs_current_ctx_ptr_f(ptr) | aperture | + return gr_fecs_current_ctx_ptr_f(u64_lo32(ptr)) | aperture | gr_fecs_current_ctx_valid_f(1); } @@ -2199,16 +2200,18 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) inst_ptr = nvgpu_inst_block_addr(g, &ucode_info->inst_blk_desc); gk20a_writel(g, gr_fecs_new_ctx_r(), - gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) | - nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, + gr_fecs_new_ctx_ptr_f(inst_ptr >> 12) | + nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, gr_fecs_new_ctx_target_sys_mem_ncoh_f(), + gr_fecs_new_ctx_target_sys_mem_coh_f(), gr_fecs_new_ctx_target_vid_mem_f()) | - gr_fecs_new_ctx_valid_m()); + gr_fecs_new_ctx_valid_m()); gk20a_writel(g, gr_fecs_arb_ctx_ptr_r(), - gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) | - nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, + gr_fecs_arb_ctx_ptr_ptr_f(inst_ptr >> 12) | + nvgpu_aperture_mask(g, &ucode_info->inst_blk_desc, gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(), + gr_fecs_arb_ctx_ptr_target_sys_mem_coh_f(), gr_fecs_arb_ctx_ptr_target_vid_mem_f())); gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7); @@ -4440,8 +4443,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) gk20a_writel(g, fb_mmu_debug_wr_r(), nvgpu_aperture_mask(g, &gr->mmu_wr_mem, - fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), - fb_mmu_debug_wr_aperture_vid_mem_f()) | + fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), + fb_mmu_debug_wr_aperture_sys_mem_coh_f(), + fb_mmu_debug_wr_aperture_vid_mem_f()) | fb_mmu_debug_wr_vol_false_f() | fb_mmu_debug_wr_addr_f(addr)); @@ -4450,8 +4454,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) gk20a_writel(g, fb_mmu_debug_rd_r(), nvgpu_aperture_mask(g, &gr->mmu_rd_mem, - fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), - fb_mmu_debug_rd_aperture_vid_mem_f()) | + fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(), + fb_mmu_debug_wr_aperture_sys_mem_coh_f(), + fb_mmu_debug_rd_aperture_vid_mem_f()) | fb_mmu_debug_rd_vol_false_f() | fb_mmu_debug_rd_addr_f(addr)); -- cgit v1.2.2