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authorDebarshi Dutta <ddutta@nvidia.com>2017-11-22 02:50:19 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-11-29 01:50:27 -0500
commit312f6c2c5f8b2ad6ab95300896ec4e7be9d5f833 (patch)
treec9a9148202fdd4f8487097d37d81c29efef6f66c /drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
parent830d3f10ca1f3d8a045542ef4548c84440a8e548 (diff)
gpu: nvgpu: remove dependency on linux header for sim_gk20a*
This patch removes linux dependencies from sim_gk20a.h under gk20a/sim_gk20a.h. The following changes are made in this patch. 1) Created a linux based structure sim_gk20a_linux that contains a common sim_gk20a struct inside it. The common struct sim_gk20a doesn't contain any linux specific structs. 2) The common struct sim_gk20a contains an added function pointer which is used to invoke gk20a_sim_esc_readl() method. 3) sim_gk20a.c is moved to nvgpu/common/linux along with a new header sim_gk20a.h that contains the definition of struct sim_gk20a_linux. 4) struct gk20a now contains a pointer of sim_gk20a instead of the entire object. The memory for this struct is allocated and initialized during gk20a_init_support() and freed during invocation of gk20_remove_support(). 5) We first obtain the pointer for struct sim_gk20a_linux from the pointer of sim_gk20a using the container_of method in order to work on the struct. JIRA NVGPU-386 Change-Id: Ic82b8702642377f82694577a53c3ca0b9c1bb2ab Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1603073 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c131
1 files changed, 68 insertions, 63 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
index d496b7b9..146b0e22 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
@@ -41,47 +41,52 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
41 g->gr.ctx_vars.dynamic = true; 41 g->gr.ctx_vars.dynamic = true;
42 g->gr.netlist = GR_NETLIST_DYNAMIC; 42 g->gr.netlist = GR_NETLIST_DYNAMIC;
43 43
44 if(!g->sim->esc_readl) {
45 nvgpu_err(g, "Invalid pointer to query function.");
46 goto fail;
47 }
48
44 /* query sizes and counts */ 49 /* query sizes and counts */
45 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0, 50 g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0,
46 &g->gr.ctx_vars.ucode.fecs.inst.count); 51 &g->gr.ctx_vars.ucode.fecs.inst.count);
47 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0, 52 g->sim->esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0,
48 &g->gr.ctx_vars.ucode.fecs.data.count); 53 &g->gr.ctx_vars.ucode.fecs.data.count);
49 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0, 54 g->sim->esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0,
50 &g->gr.ctx_vars.ucode.gpccs.inst.count); 55 &g->gr.ctx_vars.ucode.gpccs.inst.count);
51 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0, 56 g->sim->esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0,
52 &g->gr.ctx_vars.ucode.gpccs.data.count); 57 &g->gr.ctx_vars.ucode.gpccs.data.count);
53 gk20a_sim_esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp); 58 g->sim->esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp);
54 g->gr.ctx_vars.buffer_size = temp << 2; 59 g->gr.ctx_vars.buffer_size = temp << 2;
55 gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0, 60 g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0,
56 &g->gr.ctx_vars.sw_bundle_init.count); 61 &g->gr.ctx_vars.sw_bundle_init.count);
57 gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0, 62 g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0,
58 &g->gr.ctx_vars.sw_method_init.count); 63 &g->gr.ctx_vars.sw_method_init.count);
59 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0, 64 g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0,
60 &g->gr.ctx_vars.sw_ctx_load.count); 65 &g->gr.ctx_vars.sw_ctx_load.count);
61 gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0, 66 g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0,
62 &g->gr.ctx_vars.sw_veid_bundle_init.count); 67 &g->gr.ctx_vars.sw_veid_bundle_init.count);
63 68
64 gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0, 69 g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0,
65 &g->gr.ctx_vars.sw_non_ctx_load.count); 70 &g->gr.ctx_vars.sw_non_ctx_load.count);
66 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0, 71 g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0,
67 &g->gr.ctx_vars.ctxsw_regs.sys.count); 72 &g->gr.ctx_vars.ctxsw_regs.sys.count);
68 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0, 73 g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0,
69 &g->gr.ctx_vars.ctxsw_regs.gpc.count); 74 &g->gr.ctx_vars.ctxsw_regs.gpc.count);
70 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0, 75 g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0,
71 &g->gr.ctx_vars.ctxsw_regs.tpc.count); 76 &g->gr.ctx_vars.ctxsw_regs.tpc.count);
72 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0, 77 g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0,
73 &g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count); 78 &g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count);
74 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0, 79 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0,
75 &g->gr.ctx_vars.ctxsw_regs.pm_sys.count); 80 &g->gr.ctx_vars.ctxsw_regs.pm_sys.count);
76 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0, 81 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0,
77 &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count); 82 &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count);
78 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0, 83 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0,
79 &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count); 84 &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count);
80 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, 85 g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0,
81 &g->gr.ctx_vars.ctxsw_regs.ppc.count); 86 &g->gr.ctx_vars.ctxsw_regs.ppc.count);
82 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0, 87 g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0,
83 &g->gr.ctx_vars.ctxsw_regs.etpc.count); 88 &g->gr.ctx_vars.ctxsw_regs.etpc.count);
84 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, 89 g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0,
85 &g->gr.ctx_vars.ctxsw_regs.ppc.count); 90 &g->gr.ctx_vars.ctxsw_regs.ppc.count);
86 91
87 err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst); 92 err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst);
@@ -107,152 +112,152 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
107 goto fail; 112 goto fail;
108 113
109 for (i = 0; i < g->gr.ctx_vars.ucode.fecs.inst.count; i++) 114 for (i = 0; i < g->gr.ctx_vars.ucode.fecs.inst.count; i++)
110 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS", 115 g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS",
111 i, &g->gr.ctx_vars.ucode.fecs.inst.l[i]); 116 i, &g->gr.ctx_vars.ucode.fecs.inst.l[i]);
112 117
113 for (i = 0; i < g->gr.ctx_vars.ucode.fecs.data.count; i++) 118 for (i = 0; i < g->gr.ctx_vars.ucode.fecs.data.count; i++)
114 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS", 119 g->sim->esc_readl(g, "GRCTX_UCODE_DATA_FECS",
115 i, &g->gr.ctx_vars.ucode.fecs.data.l[i]); 120 i, &g->gr.ctx_vars.ucode.fecs.data.l[i]);
116 121
117 for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.inst.count; i++) 122 for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.inst.count; i++)
118 gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS", 123 g->sim->esc_readl(g, "GRCTX_UCODE_INST_GPCCS",
119 i, &g->gr.ctx_vars.ucode.gpccs.inst.l[i]); 124 i, &g->gr.ctx_vars.ucode.gpccs.inst.l[i]);
120 125
121 for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.data.count; i++) 126 for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.data.count; i++)
122 gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS", 127 g->sim->esc_readl(g, "GRCTX_UCODE_DATA_GPCCS",
123 i, &g->gr.ctx_vars.ucode.gpccs.data.l[i]); 128 i, &g->gr.ctx_vars.ucode.gpccs.data.l[i]);
124 129
125 for (i = 0; i < g->gr.ctx_vars.sw_bundle_init.count; i++) { 130 for (i = 0; i < g->gr.ctx_vars.sw_bundle_init.count; i++) {
126 struct av_gk20a *l = g->gr.ctx_vars.sw_bundle_init.l; 131 struct av_gk20a *l = g->gr.ctx_vars.sw_bundle_init.l;
127 gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR", 132 g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR",
128 i, &l[i].addr); 133 i, &l[i].addr);
129 gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE", 134 g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE",
130 i, &l[i].value); 135 i, &l[i].value);
131 } 136 }
132 137
133 for (i = 0; i < g->gr.ctx_vars.sw_method_init.count; i++) { 138 for (i = 0; i < g->gr.ctx_vars.sw_method_init.count; i++) {
134 struct av_gk20a *l = g->gr.ctx_vars.sw_method_init.l; 139 struct av_gk20a *l = g->gr.ctx_vars.sw_method_init.l;
135 gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR", 140 g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR",
136 i, &l[i].addr); 141 i, &l[i].addr);
137 gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE", 142 g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE",
138 i, &l[i].value); 143 i, &l[i].value);
139 } 144 }
140 145
141 for (i = 0; i < g->gr.ctx_vars.sw_ctx_load.count; i++) { 146 for (i = 0; i < g->gr.ctx_vars.sw_ctx_load.count; i++) {
142 struct aiv_gk20a *l = g->gr.ctx_vars.sw_ctx_load.l; 147 struct aiv_gk20a *l = g->gr.ctx_vars.sw_ctx_load.l;
143 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR", 148 g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR",
144 i, &l[i].addr); 149 i, &l[i].addr);
145 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX", 150 g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX",
146 i, &l[i].index); 151 i, &l[i].index);
147 gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE", 152 g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE",
148 i, &l[i].value); 153 i, &l[i].value);
149 } 154 }
150 155
151 for (i = 0; i < g->gr.ctx_vars.sw_non_ctx_load.count; i++) { 156 for (i = 0; i < g->gr.ctx_vars.sw_non_ctx_load.count; i++) {
152 struct av_gk20a *l = g->gr.ctx_vars.sw_non_ctx_load.l; 157 struct av_gk20a *l = g->gr.ctx_vars.sw_non_ctx_load.l;
153 gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:REG", 158 g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG:REG",
154 i, &l[i].addr); 159 i, &l[i].addr);
155 gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE", 160 g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE",
156 i, &l[i].value); 161 i, &l[i].value);
157 } 162 }
158 163
159 for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) { 164 for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) {
160 struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l; 165 struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l;
161 166
162 gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR", 167 g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR",
163 i, &l[i].addr); 168 i, &l[i].addr);
164 gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE", 169 g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE",
165 i, &l[i].value); 170 i, &l[i].value);
166 } 171 }
167 172
168 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) { 173 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) {
169 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l; 174 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l;
170 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR", 175 g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR",
171 i, &l[i].addr); 176 i, &l[i].addr);
172 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX", 177 g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX",
173 i, &l[i].index); 178 i, &l[i].index);
174 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE", 179 g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE",
175 i, &l[i].value); 180 i, &l[i].value);
176 } 181 }
177 182
178 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.gpc.count; i++) { 183 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.gpc.count; i++) {
179 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.gpc.l; 184 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.gpc.l;
180 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR", 185 g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR",
181 i, &l[i].addr); 186 i, &l[i].addr);
182 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX", 187 g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX",
183 i, &l[i].index); 188 i, &l[i].index);
184 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE", 189 g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE",
185 i, &l[i].value); 190 i, &l[i].value);
186 } 191 }
187 192
188 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.tpc.count; i++) { 193 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.tpc.count; i++) {
189 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.tpc.l; 194 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.tpc.l;
190 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR", 195 g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR",
191 i, &l[i].addr); 196 i, &l[i].addr);
192 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX", 197 g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX",
193 i, &l[i].index); 198 i, &l[i].index);
194 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE", 199 g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE",
195 i, &l[i].value); 200 i, &l[i].value);
196 } 201 }
197 202
198 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.ppc.count; i++) { 203 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.ppc.count; i++) {
199 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.ppc.l; 204 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.ppc.l;
200 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR", 205 g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR",
201 i, &l[i].addr); 206 i, &l[i].addr);
202 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX", 207 g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX",
203 i, &l[i].index); 208 i, &l[i].index);
204 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE", 209 g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE",
205 i, &l[i].value); 210 i, &l[i].value);
206 } 211 }
207 212
208 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count; i++) { 213 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count; i++) {
209 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l; 214 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l;
210 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR", 215 g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR",
211 i, &l[i].addr); 216 i, &l[i].addr);
212 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX", 217 g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX",
213 i, &l[i].index); 218 i, &l[i].index);
214 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE", 219 g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE",
215 i, &l[i].value); 220 i, &l[i].value);
216 } 221 }
217 222
218 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_sys.count; i++) { 223 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_sys.count; i++) {
219 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_sys.l; 224 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_sys.l;
220 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR", 225 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR",
221 i, &l[i].addr); 226 i, &l[i].addr);
222 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX", 227 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX",
223 i, &l[i].index); 228 i, &l[i].index);
224 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE", 229 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE",
225 i, &l[i].value); 230 i, &l[i].value);
226 } 231 }
227 232
228 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_gpc.count; i++) { 233 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_gpc.count; i++) {
229 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_gpc.l; 234 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_gpc.l;
230 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR", 235 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR",
231 i, &l[i].addr); 236 i, &l[i].addr);
232 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX", 237 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX",
233 i, &l[i].index); 238 i, &l[i].index);
234 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE", 239 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE",
235 i, &l[i].value); 240 i, &l[i].value);
236 } 241 }
237 242
238 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_tpc.count; i++) { 243 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_tpc.count; i++) {
239 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_tpc.l; 244 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_tpc.l;
240 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR", 245 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR",
241 i, &l[i].addr); 246 i, &l[i].addr);
242 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX", 247 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX",
243 i, &l[i].index); 248 i, &l[i].index);
244 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE", 249 g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE",
245 i, &l[i].value); 250 i, &l[i].value);
246 } 251 }
247 252
248 gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_ETPC"); 253 gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_ETPC");
249 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.etpc.count; i++) { 254 for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.etpc.count; i++) {
250 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.etpc.l; 255 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.etpc.l;
251 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR", 256 g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR",
252 i, &l[i].addr); 257 i, &l[i].addr);
253 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX", 258 g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX",
254 i, &l[i].index); 259 i, &l[i].index);
255 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE", 260 g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE",
256 i, &l[i].value); 261 i, &l[i].value);
257 gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, 262 gk20a_dbg(gpu_dbg_info | gpu_dbg_fn,
258 "addr:0x%#08x index:0x%08x value:0x%08x", 263 "addr:0x%#08x index:0x%08x value:0x%08x",
@@ -261,7 +266,7 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
261 266
262 g->gr.ctx_vars.valid = true; 267 g->gr.ctx_vars.valid = true;
263 268
264 gk20a_sim_esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0, 269 g->sim->esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0,
265 &g->gr.ctx_vars.regs_base_index); 270 &g->gr.ctx_vars.regs_base_index);
266 271
267 gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "finished querying grctx info from chiplib"); 272 gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "finished querying grctx info from chiplib");
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:54:25 -0400