From 312f6c2c5f8b2ad6ab95300896ec4e7be9d5f833 Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Wed, 22 Nov 2017 13:20:19 +0530 Subject: gpu: nvgpu: remove dependency on linux header for sim_gk20a* This patch removes linux dependencies from sim_gk20a.h under gk20a/sim_gk20a.h. The following changes are made in this patch. 1) Created a linux based structure sim_gk20a_linux that contains a common sim_gk20a struct inside it. The common struct sim_gk20a doesn't contain any linux specific structs. 2) The common struct sim_gk20a contains an added function pointer which is used to invoke gk20a_sim_esc_readl() method. 3) sim_gk20a.c is moved to nvgpu/common/linux along with a new header sim_gk20a.h that contains the definition of struct sim_gk20a_linux. 4) struct gk20a now contains a pointer of sim_gk20a instead of the entire object. The memory for this struct is allocated and initialized during gk20a_init_support() and freed during invocation of gk20_remove_support(). 5) We first obtain the pointer for struct sim_gk20a_linux from the pointer of sim_gk20a using the container_of method in order to work on the struct. JIRA NVGPU-386 Change-Id: Ic82b8702642377f82694577a53c3ca0b9c1bb2ab Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1603073 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | 131 +++++++++++++++-------------- 1 file changed, 68 insertions(+), 63 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c') diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c index d496b7b9..146b0e22 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c @@ -41,47 +41,52 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) g->gr.ctx_vars.dynamic = true; g->gr.netlist = GR_NETLIST_DYNAMIC; + if(!g->sim->esc_readl) { + nvgpu_err(g, "Invalid pointer to query function."); + goto fail; + } + /* query sizes and counts */ - gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0, &g->gr.ctx_vars.ucode.fecs.inst.count); - gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0, &g->gr.ctx_vars.ucode.fecs.data.count); - gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0, &g->gr.ctx_vars.ucode.gpccs.inst.count); - gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0, &g->gr.ctx_vars.ucode.gpccs.data.count); - gk20a_sim_esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp); + g->sim->esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp); g->gr.ctx_vars.buffer_size = temp << 2; - gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0, + g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0, &g->gr.ctx_vars.sw_bundle_init.count); - gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0, + g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0, &g->gr.ctx_vars.sw_method_init.count); - gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0, + g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0, &g->gr.ctx_vars.sw_ctx_load.count); - gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0, + g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0, &g->gr.ctx_vars.sw_veid_bundle_init.count); - gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0, + g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0, &g->gr.ctx_vars.sw_non_ctx_load.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.sys.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.gpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.tpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.pm_sys.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.ppc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.etpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.ppc.count); err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst); @@ -107,152 +112,152 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) goto fail; for (i = 0; i < g->gr.ctx_vars.ucode.fecs.inst.count; i++) - gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS", + g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS", i, &g->gr.ctx_vars.ucode.fecs.inst.l[i]); for (i = 0; i < g->gr.ctx_vars.ucode.fecs.data.count; i++) - gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS", + g->sim->esc_readl(g, "GRCTX_UCODE_DATA_FECS", i, &g->gr.ctx_vars.ucode.fecs.data.l[i]); for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.inst.count; i++) - gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS", + g->sim->esc_readl(g, "GRCTX_UCODE_INST_GPCCS", i, &g->gr.ctx_vars.ucode.gpccs.inst.l[i]); for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.data.count; i++) - gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS", + g->sim->esc_readl(g, "GRCTX_UCODE_DATA_GPCCS", i, &g->gr.ctx_vars.ucode.gpccs.data.l[i]); for (i = 0; i < g->gr.ctx_vars.sw_bundle_init.count; i++) { struct av_gk20a *l = g->gr.ctx_vars.sw_bundle_init.l; - gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR", + g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE", + g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.sw_method_init.count; i++) { struct av_gk20a *l = g->gr.ctx_vars.sw_method_init.l; - gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR", + g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE", + g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.sw_ctx_load.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.sw_ctx_load.l; - gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR", + g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX", + g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE", + g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.sw_non_ctx_load.count; i++) { struct av_gk20a *l = g->gr.ctx_vars.sw_non_ctx_load.l; - gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:REG", + g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG:REG", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE", + g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) { struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l; - gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR", + g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE", + g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.gpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.gpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.tpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.tpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.ppc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.ppc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_sys.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_sys.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_gpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_gpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_tpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_tpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE", i, &l[i].value); } gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_ETPC"); for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.etpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.etpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE", i, &l[i].value); gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "addr:0x%#08x index:0x%08x value:0x%08x", @@ -261,7 +266,7 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) g->gr.ctx_vars.valid = true; - gk20a_sim_esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0, + g->sim->esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0, &g->gr.ctx_vars.regs_base_index); gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "finished querying grctx info from chiplib"); -- cgit v1.2.2