gpu: nvgpu: support CAU ctxsw list

CAU (Counter Aggregation Unit) registers might be split out from SMPC registers
and moved into their own list on some platforms

In gr_gk20a_init_ctx_vars_fw() add support to check if pm_cau list is available
If list is available, count will be set to non-zero here

In add_ctxsw_buffer_map_entries_gpcs(), parse the pm_cau list if count is
non-zero

Bug 2139870

Change-Id: Ia630e7d03481a6f927c6739d28ebfe49f221326f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1733208
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Braun (SW-GPU) <matthewb@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h
index d8fb8dcd..afc3e9df 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h
@@ -105,6 +105,7 @@ union __max_name {
 #define NETLIST_REGIONID_CTXREG_PMROP           31
 #define NETLIST_REGIONID_CTXREG_PMUCGPC         32
 #define NETLIST_REGIONID_CTXREG_ETPC            33
+#define NETLIST_REGIONID_NVPERF_PMCAU           35
 
 struct netlist_region {
         u32 region_id;