diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2014-10-01 11:53:49 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:12:10 -0400 |
commit | f8f6b298848ed05ad83ce107ff8a4fff0b37dd2d (patch) | |
tree | 554d121fbbc47745556cd6a99c6b5d6258951b80 /drivers/gpu/nvgpu/gk20a/gk20a.h | |
parent | 6275bbb33bb0f72cc03c7e68d8186b36c96ee854 (diff) |
gpu: nvgpu: support config of TPC FUSE dynamically
Follow steps below to config active TPC number:
echo 1 > /sys/devices/platform/host1x/gpu.0/force_idle
echo 0x1/0x2/0x3 > /sys/devices/platform/host1x/gpu.0/tpc_fs_mask
echo 0 > /sys/devices/platform/host1x/gpu.0/force_idle
where,
0x1 : disable TPC1
0x2 : disable TPC0
0x3 : both TPCs active
Also, add API set_gpc_tpc_mask to update the TPCs and call this
API after update to sysfs "tpc_fs_mask"
Once fuses are updated for new TPC settings, we need to
reconfigure GR and golden_image. Hence disable gr->sw_ready
and golden_image_initialized flags.
Also, initialize gr->tpc_count = 0 each time in
gr_gk20a_init_gr_config(), otherwise it goes on adding tpc count
Bug 1513685
Change-Id: Ib50bafef08664262f8426ac0d6cbad74b32c5909
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/552606
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 3f070a58..49038a0f 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -125,6 +125,7 @@ struct gpu_ops { | |||
125 | u32 reg_offset); | 125 | u32 reg_offset); |
126 | int (*load_ctxsw_ucode)(struct gk20a *g); | 126 | int (*load_ctxsw_ucode)(struct gk20a *g); |
127 | u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); | 127 | u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); |
128 | void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); | ||
128 | void (*free_channel_ctx)(struct channel_gk20a *c); | 129 | void (*free_channel_ctx)(struct channel_gk20a *c); |
129 | int (*alloc_obj_ctx)(struct channel_gk20a *c, | 130 | int (*alloc_obj_ctx)(struct channel_gk20a *c, |
130 | struct nvgpu_alloc_obj_ctx_args *args); | 131 | struct nvgpu_alloc_obj_ctx_args *args); |