From f8f6b298848ed05ad83ce107ff8a4fff0b37dd2d Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 1 Oct 2014 21:23:49 +0530 Subject: gpu: nvgpu: support config of TPC FUSE dynamically Follow steps below to config active TPC number: echo 1 > /sys/devices/platform/host1x/gpu.0/force_idle echo 0x1/0x2/0x3 > /sys/devices/platform/host1x/gpu.0/tpc_fs_mask echo 0 > /sys/devices/platform/host1x/gpu.0/force_idle where, 0x1 : disable TPC1 0x2 : disable TPC0 0x3 : both TPCs active Also, add API set_gpc_tpc_mask to update the TPCs and call this API after update to sysfs "tpc_fs_mask" Once fuses are updated for new TPC settings, we need to reconfigure GR and golden_image. Hence disable gr->sw_ready and golden_image_initialized flags. Also, initialize gr->tpc_count = 0 each time in gr_gk20a_init_gr_config(), otherwise it goes on adding tpc count Bug 1513685 Change-Id: Ib50bafef08664262f8426ac0d6cbad74b32c5909 Signed-off-by: Kevin Huang Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/552606 Reviewed-by: Sachin Nikam --- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 3f070a58..49038a0f 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -125,6 +125,7 @@ struct gpu_ops { u32 reg_offset); int (*load_ctxsw_ucode)(struct gk20a *g); u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); + void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); void (*free_channel_ctx)(struct channel_gk20a *c); int (*alloc_obj_ctx)(struct channel_gk20a *c, struct nvgpu_alloc_obj_ctx_args *args); -- cgit v1.2.2