gpu: nvgpu: add handle_tpc_sm_ecc_exception gr ops

Needed to handle t19x sm ecc errors per tpc

JIRA GPUT19X-75
JIRA GPUT19X-109

Change-Id: I921615dd5f551f34cdf55c1b085b16f562f16eb0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514044
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 95b93496..e30a89fe 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -304,6 +304,10 @@ struct gpu_ops {
                                          u32 global_esr);
                 void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc,
                                          u32 *esr_sm_sel);
+                int (*handle_tpc_sm_ecc_exception)(struct gk20a *g,
+                        u32 gpc, u32 tpc,
+                        bool *post_event, struct channel_gk20a *fault_ch,
+                        u32 *hww_global_esr);
                 int (*handle_sm_exception)(struct gk20a *g,
                         u32 gpc, u32 tpc, u32 sm,
                         bool *post_event, struct channel_gk20a *fault_ch,