From 84f712dee8b582dd7d2a19345c621a2ae3bd6292 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 5 Jul 2017 12:21:18 -0700 Subject: gpu: nvgpu: add handle_tpc_sm_ecc_exception gr ops Needed to handle t19x sm ecc errors per tpc JIRA GPUT19X-75 JIRA GPUT19X-109 Change-Id: I921615dd5f551f34cdf55c1b085b16f562f16eb0 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1514044 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/gk20a.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 95b93496..e30a89fe 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -304,6 +304,10 @@ struct gpu_ops { u32 global_esr); void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, u32 *esr_sm_sel); + int (*handle_tpc_sm_ecc_exception)(struct gk20a *g, + u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr); int (*handle_sm_exception)(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, bool *post_event, struct channel_gk20a *fault_ch, -- cgit v1.2.2