gpu: nvgpu: Per-chip interrupt processing

Move accesses to MC registers under HAL so that they can be
reimplemented per chip.

Do chip detection and HAL initialization only once.

Bug 1567274

Change-Id: I20bf2f439d267d284bfd536f1a1dfb5d5a2dce4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590385

1 files changed, 11 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 5669e1c5..a111a040 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -29,7 +29,8 @@ struct acr_gm20b;
 
 #include <linux/sched.h>
 #include <linux/spinlock.h>
-#include <uapi/linux/nvgpu.h>
+#include <linux/nvgpu.h>
+#include <linux/irqreturn.h>
 #include <linux/tegra-soc.h>
 
 #include "../../../arch/arm/mach-tegra/iomap.h"
@@ -335,6 +336,13 @@ struct gpu_ops {
                                 *get_qctl_whitelist_ranges)(void);
                 int (*get_qctl_whitelist_ranges_count)(void);
         } regops;
+        struct {
+                void (*intr_enable)(struct gk20a *g);
+                irqreturn_t (*isr_stall)(struct gk20a *g);
+                irqreturn_t (*isr_nonstall)(struct gk20a *g);
+                irqreturn_t (*isr_thread_stall)(struct gk20a *g);
+                irqreturn_t (*isr_thread_nonstall)(struct gk20a *g);
+        } mc;
 };
 
 struct gk20a {
@@ -734,6 +742,8 @@ gk20a_request_firmware(struct gk20a *g, const char *fw_name);
 
 int gk20a_init_gpu_characteristics(struct gk20a *g);
 
+void gk20a_pbus_isr(struct gk20a *g);
+
 int gk20a_user_init(struct platform_device *dev);
 void gk20a_user_deinit(struct platform_device *dev);