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authorDeepak Nibade <dnibade@nvidia.com>2016-07-20 03:09:12 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-08-10 14:17:58 -0400
commit59a115f3fe6076de4c9af69de836cc82d6430544 (patch)
tree18af9e6080ee1306b1737ac74f392d88150e7a3c /drivers/gpu/nvgpu/gk20a/gk20a.h
parent118809f4bd07af20df2b6c012828834695a5fccf (diff)
gpu: nvgpu: post bpt events after processing
We currently post bpt events (bpt.int and bpt.pause) even before we process and clear the interrupts and this could cause races with UMD Fix this by posting bpt events only after we are done processing the interrupts Bug 200209410 Change-Id: Ic3ff7148189fccb796cb6175d6d22ac25a4097fb Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1184109 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 7eb98a2c..6f735af9 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -264,7 +264,8 @@ struct gpu_ops {
264 bool *early_exit, bool *ignore_debugger); 264 bool *early_exit, bool *ignore_debugger);
265 u32 (*mask_hww_warp_esr)(u32 hww_warp_esr); 265 u32 (*mask_hww_warp_esr)(u32 hww_warp_esr);
266 int (*handle_sm_exception)(struct gk20a *g, u32 gpc, u32 tpc, 266 int (*handle_sm_exception)(struct gk20a *g, u32 gpc, u32 tpc,
267 bool *post_event, struct channel_gk20a *fault_ch); 267 bool *post_event, struct channel_gk20a *fault_ch,
268 u32 *hww_global_esr);
268 int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, 269 int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc,
269 bool *post_event); 270 bool *post_event);
270 void (*create_gr_sysfs)(struct device *dev); 271 void (*create_gr_sysfs)(struct device *dev);