gpu: nvgpu: add fifo ops for intr_0_error_mask

This change is required to support t19x mmu fault

Change-Id: I3953dcf02c71ace606ba81896e56ea98683eb2ca
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313482
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 73123fa9..a4f0799a 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -450,6 +450,7 @@ struct gpu_ops {
                 void (*dump_channel_status_ramfc)(struct gk20a *g,
                                 struct gk20a_debug_output *o, u32 hw_chid,
                                 struct ch_state *ch_state);
+                u32 (*intr_0_error_mask)(struct gk20a *g);
         } fifo;
         struct pmu_v {
                 /*used for change of enum zbc update cmd id from ver 0 to ver1*/