From 50f371f891c889c782187036c31132fa94c573ac Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 15:24:17 -0800 Subject: gpu: nvgpu: add fifo ops for intr_0_error_mask This change is required to support t19x mmu fault Change-Id: I3953dcf02c71ace606ba81896e56ea98683eb2ca Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313482 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 73123fa9..a4f0799a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -450,6 +450,7 @@ struct gpu_ops { void (*dump_channel_status_ramfc)(struct gk20a *g, struct gk20a_debug_output *o, u32 hw_chid, struct ch_state *ch_state); + u32 (*intr_0_error_mask)(struct gk20a *g); } fifo; struct pmu_v { /*used for change of enum zbc update cmd id from ver 0 to ver1*/ -- cgit v1.2.2