gpu: nvgpu: add resume_single_sm gr ops

This is required to support multiple SM and t19x
sm register address changes

JIRA GPUT19X-75

Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512216
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f94be010..aae54cc2 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -375,6 +375,8 @@ struct gpu_ops {
                                 u32 global_esr_mask, bool check_errors);
                 void (*suspend_all_sms)(struct gk20a *g,
                                 u32 global_esr_mask, bool check_errors);
+                void (*resume_single_sm)(struct gk20a *g,
+                                u32 gpc, u32 tpc, u32 sm);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);