From 1ab0eec6eae303fa2b2f7cc97b78aed4a9f895e5 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sun, 2 Jul 2017 16:43:31 -0700 Subject: gpu: nvgpu: add resume_single_sm gr ops This is required to support multiple SM and t19x sm register address changes JIRA GPUT19X-75 Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1512216 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index f94be010..aae54cc2 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -375,6 +375,8 @@ struct gpu_ops { u32 global_esr_mask, bool check_errors); void (*suspend_all_sms)(struct gk20a *g, u32 global_esr_mask, bool check_errors); + void (*resume_single_sm)(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm); } gr; struct { void (*init_hw)(struct gk20a *g); -- cgit v1.2.2