diff options
author | Deepak Goyal <dgoyal@nvidia.com> | 2018-09-14 02:15:19 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-27 01:24:52 -0400 |
commit | 34732a14b22f09d8f9d52f756612178f0313f120 (patch) | |
tree | 94f634efcad3179ddbca82dedaf82dfe8f099030 /drivers/gpu/nvgpu/gk20a/gk20a.c | |
parent | 991179f29cea8ab8272465789496c2f15bad6240 (diff) |
nvgpu: gpu: Support multiple tpc-pg masks.
- TPC powergating should be done before
calling gk20a_enable_gr_hw.
gk20a_enable_gr_hw() issues a GR engine reset.
Without this fix, enabling 1 TPC from each PES
causes ctxsw timeout error while running GFX Benchmark.
- Adds valid tpc-pg mask for 1/2/3/4 active TPC configs.
TPC Config - TPC-MASK
4 TPC configuration - 0x0
3 TPC configuration - 0x1/0x2/0x4/0x8
2 TPC configuration - 0x5/0x9/0x6/0xa
- We should not write to gr_fe_tpc_pesmask_r()
as part of TPC-PG sequence. This register is for
debug purpose only.
Bug 200442360
Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809772
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 9958d24f..1cad8dcb 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -259,9 +259,28 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
259 | 259 | ||
260 | g->ops.mc.intr_enable(g); | 260 | g->ops.mc.intr_enable(g); |
261 | 261 | ||
262 | /* | ||
263 | * Overwrite can_tpc_powergate to false if the chip is ES fused and | ||
264 | * already optimized with some TPCs already floorswept | ||
265 | * via fuse. We will not support TPC-PG in those cases. | ||
266 | */ | ||
267 | |||
268 | if (g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0) != 0x0) { | ||
269 | g->can_tpc_powergate = false; | ||
270 | g->tpc_pg_mask = 0x0; | ||
271 | } | ||
272 | |||
273 | nvgpu_mutex_acquire(&g->tpc_pg_lock); | ||
274 | |||
275 | if (g->can_tpc_powergate) { | ||
276 | if (g->ops.gr.powergate_tpc != NULL) | ||
277 | g->ops.gr.powergate_tpc(g); | ||
278 | } | ||
279 | |||
262 | err = gk20a_enable_gr_hw(g); | 280 | err = gk20a_enable_gr_hw(g); |
263 | if (err) { | 281 | if (err) { |
264 | nvgpu_err(g, "failed to enable gr"); | 282 | nvgpu_err(g, "failed to enable gr"); |
283 | nvgpu_mutex_release(&g->tpc_pg_lock); | ||
265 | goto done; | 284 | goto done; |
266 | } | 285 | } |
267 | 286 | ||
@@ -271,6 +290,7 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
271 | } | 290 | } |
272 | if (err) { | 291 | if (err) { |
273 | nvgpu_err(g, "failed to init pmu ucode"); | 292 | nvgpu_err(g, "failed to init pmu ucode"); |
293 | nvgpu_mutex_release(&g->tpc_pg_lock); | ||
274 | goto done; | 294 | goto done; |
275 | } | 295 | } |
276 | } | 296 | } |
@@ -279,6 +299,7 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
279 | err = gk20a_init_pstate_support(g); | 299 | err = gk20a_init_pstate_support(g); |
280 | if (err) { | 300 | if (err) { |
281 | nvgpu_err(g, "failed to init pstates"); | 301 | nvgpu_err(g, "failed to init pstates"); |
302 | nvgpu_mutex_release(&g->tpc_pg_lock); | ||
282 | goto done; | 303 | goto done; |
283 | } | 304 | } |
284 | } | 305 | } |
@@ -296,18 +317,11 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
296 | err = nvgpu_init_pmu_support(g); | 317 | err = nvgpu_init_pmu_support(g); |
297 | if (err) { | 318 | if (err) { |
298 | nvgpu_err(g, "failed to init gk20a pmu"); | 319 | nvgpu_err(g, "failed to init gk20a pmu"); |
320 | nvgpu_mutex_release(&g->tpc_pg_lock); | ||
299 | goto done; | 321 | goto done; |
300 | } | 322 | } |
301 | } | 323 | } |
302 | 324 | ||
303 | nvgpu_mutex_acquire(&g->tpc_pg_lock); | ||
304 | |||
305 | if (g->can_tpc_powergate) { | ||
306 | if (g->ops.gr.powergate_tpc != NULL) { | ||
307 | g->ops.gr.powergate_tpc(g); | ||
308 | } | ||
309 | } | ||
310 | |||
311 | err = gk20a_init_gr_support(g); | 325 | err = gk20a_init_gr_support(g); |
312 | if (err) { | 326 | if (err) { |
313 | nvgpu_err(g, "failed to init gk20a gr"); | 327 | nvgpu_err(g, "failed to init gk20a gr"); |