From 34732a14b22f09d8f9d52f756612178f0313f120 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Fri, 14 Sep 2018 11:45:19 +0530 Subject: nvgpu: gpu: Support multiple tpc-pg masks. - TPC powergating should be done before calling gk20a_enable_gr_hw. gk20a_enable_gr_hw() issues a GR engine reset. Without this fix, enabling 1 TPC from each PES causes ctxsw timeout error while running GFX Benchmark. - Adds valid tpc-pg mask for 1/2/3/4 active TPC configs. TPC Config - TPC-MASK 4 TPC configuration - 0x0 3 TPC configuration - 0x1/0x2/0x4/0x8 2 TPC configuration - 0x5/0x9/0x6/0xa - We should not write to gr_fe_tpc_pesmask_r() as part of TPC-PG sequence. This register is for debug purpose only. Bug 200442360 Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1809772 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 9958d24f..1cad8dcb 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -259,9 +259,28 @@ int gk20a_finalize_poweron(struct gk20a *g) g->ops.mc.intr_enable(g); + /* + * Overwrite can_tpc_powergate to false if the chip is ES fused and + * already optimized with some TPCs already floorswept + * via fuse. We will not support TPC-PG in those cases. + */ + + if (g->ops.fuse.fuse_status_opt_tpc_gpc(g, 0) != 0x0) { + g->can_tpc_powergate = false; + g->tpc_pg_mask = 0x0; + } + + nvgpu_mutex_acquire(&g->tpc_pg_lock); + + if (g->can_tpc_powergate) { + if (g->ops.gr.powergate_tpc != NULL) + g->ops.gr.powergate_tpc(g); + } + err = gk20a_enable_gr_hw(g); if (err) { nvgpu_err(g, "failed to enable gr"); + nvgpu_mutex_release(&g->tpc_pg_lock); goto done; } @@ -271,6 +290,7 @@ int gk20a_finalize_poweron(struct gk20a *g) } if (err) { nvgpu_err(g, "failed to init pmu ucode"); + nvgpu_mutex_release(&g->tpc_pg_lock); goto done; } } @@ -279,6 +299,7 @@ int gk20a_finalize_poweron(struct gk20a *g) err = gk20a_init_pstate_support(g); if (err) { nvgpu_err(g, "failed to init pstates"); + nvgpu_mutex_release(&g->tpc_pg_lock); goto done; } } @@ -296,18 +317,11 @@ int gk20a_finalize_poweron(struct gk20a *g) err = nvgpu_init_pmu_support(g); if (err) { nvgpu_err(g, "failed to init gk20a pmu"); + nvgpu_mutex_release(&g->tpc_pg_lock); goto done; } } - nvgpu_mutex_acquire(&g->tpc_pg_lock); - - if (g->can_tpc_powergate) { - if (g->ops.gr.powergate_tpc != NULL) { - g->ops.gr.powergate_tpc(g); - } - } - err = gk20a_init_gr_support(g); if (err) { nvgpu_err(g, "failed to init gk20a gr"); -- cgit v1.2.2