diff options
author | Peter Daifuku <pdaifuku@nvidia.com> | 2016-03-09 22:10:20 -0500 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-07 14:05:49 -0400 |
commit | 37155b65f1dd6039bdef92f513d86640956bc12c (patch) | |
tree | 1deb57523c3acc445996c642da6ac96e1cf7c355 /drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |
parent | 6675c03603669c667c6ffec34567eaf101a2d09d (diff) |
gpu: nvgpu: support for hwpm context switching
Add support for hwpm context switching
Bug 1648200
Change-Id: I482899bf165cd2ef24bb8617be16df01218e462f
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1120450
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 47 |
1 files changed, 45 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index 1ee0189b..d087d89e 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |||
@@ -457,6 +457,9 @@ static int nvgpu_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s, | |||
457 | static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | 457 | static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, |
458 | struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args *args); | 458 | struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args *args); |
459 | 459 | ||
460 | static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | ||
461 | struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args); | ||
462 | |||
460 | static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( | 463 | static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( |
461 | struct dbg_session_gk20a *dbg_s, | 464 | struct dbg_session_gk20a *dbg_s, |
462 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args); | 465 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args); |
@@ -582,6 +585,11 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
582 | (struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args *)buf); | 585 | (struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args *)buf); |
583 | break; | 586 | break; |
584 | 587 | ||
588 | case NVGPU_DBG_GPU_IOCTL_HWPM_CTXSW_MODE: | ||
589 | err = nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(dbg_s, | ||
590 | (struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *)buf); | ||
591 | break; | ||
592 | |||
585 | case NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS: | 593 | case NVGPU_DBG_GPU_IOCTL_SUSPEND_RESUME_ALL_SMS: |
586 | err = nvgpu_dbg_gpu_ioctl_suspend_resume_sm(dbg_s, | 594 | err = nvgpu_dbg_gpu_ioctl_suspend_resume_sm(dbg_s, |
587 | (struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *)buf); | 595 | (struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *)buf); |
@@ -880,7 +888,7 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | |||
880 | ch_gk20a = dbg_s->ch; | 888 | ch_gk20a = dbg_s->ch; |
881 | 889 | ||
882 | if (!ch_gk20a) { | 890 | if (!ch_gk20a) { |
883 | gk20a_err(dev_from_gk20a(dbg_s->g), | 891 | gk20a_err(dev_from_gk20a(g), |
884 | "no bound channel for smpc ctxsw mode update\n"); | 892 | "no bound channel for smpc ctxsw mode update\n"); |
885 | err = -EINVAL; | 893 | err = -EINVAL; |
886 | goto clean_up; | 894 | goto clean_up; |
@@ -889,13 +897,48 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | |||
889 | err = gr_gk20a_update_smpc_ctxsw_mode(g, ch_gk20a, | 897 | err = gr_gk20a_update_smpc_ctxsw_mode(g, ch_gk20a, |
890 | args->mode == NVGPU_DBG_GPU_SMPC_CTXSW_MODE_CTXSW); | 898 | args->mode == NVGPU_DBG_GPU_SMPC_CTXSW_MODE_CTXSW); |
891 | if (err) { | 899 | if (err) { |
892 | gk20a_err(dev_from_gk20a(dbg_s->g), | 900 | gk20a_err(dev_from_gk20a(g), |
893 | "error (%d) during smpc ctxsw mode update\n", err); | 901 | "error (%d) during smpc ctxsw mode update\n", err); |
894 | goto clean_up; | 902 | goto clean_up; |
895 | } | 903 | } |
896 | 904 | ||
897 | err = g->ops.regops.apply_smpc_war(dbg_s); | 905 | err = g->ops.regops.apply_smpc_war(dbg_s); |
906 | clean_up: | ||
907 | mutex_unlock(&g->dbg_sessions_lock); | ||
908 | return err; | ||
909 | } | ||
910 | |||
911 | static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | ||
912 | struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args) | ||
913 | { | ||
914 | int err; | ||
915 | struct gk20a *g = get_gk20a(dbg_s->pdev); | ||
916 | struct channel_gk20a *ch_gk20a; | ||
898 | 917 | ||
918 | gk20a_dbg_fn("%s pm ctxsw mode = %d", | ||
919 | dev_name(dbg_s->dev), args->mode); | ||
920 | |||
921 | /* Take the global lock, since we'll be doing global regops */ | ||
922 | mutex_lock(&g->dbg_sessions_lock); | ||
923 | |||
924 | ch_gk20a = dbg_s->ch; | ||
925 | |||
926 | if (!ch_gk20a) { | ||
927 | gk20a_err(dev_from_gk20a(g), | ||
928 | "no bound channel for pm ctxsw mode update\n"); | ||
929 | err = -EINVAL; | ||
930 | goto clean_up; | ||
931 | } | ||
932 | |||
933 | err = gr_gk20a_update_hwpm_ctxsw_mode(g, ch_gk20a, | ||
934 | args->mode == NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW); | ||
935 | if (err) | ||
936 | gk20a_err(dev_from_gk20a(g), | ||
937 | "error (%d) during pm ctxsw mode update\n", err); | ||
938 | |||
939 | /* gk20a would require a WAR to set the core PM_ENABLE bit, not | ||
940 | * added here with gk20a being deprecated | ||
941 | */ | ||
899 | clean_up: | 942 | clean_up: |
900 | mutex_unlock(&g->dbg_sessions_lock); | 943 | mutex_unlock(&g->dbg_sessions_lock); |
901 | return err; | 944 | return err; |