diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-04-10 13:47:02 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-13 16:44:41 -0400 |
commit | 22426a5452ba943ac48867722fb0927baf66d4ac (patch) | |
tree | 4595c635cc920e4ba2d540a6e070b89e3037c28e /drivers/gpu/nvgpu/gk20a/clk_gk20a.c | |
parent | a0fa2b0258dafcd7a2450ab5366a49663b1d2e89 (diff) |
gpu: nvgpu: gk20a: Use new delay APIs
Use platform agnostic delay functions instead of Linux kernel APIs.
This allows removing dependency to Linux header linux/delay.h. At the
same time remove #include lines for other unused Linux headers.
JIRA NVGPU-16
Change-Id: I46b9ccb80e0b67efb86ec85676e5a55ff835c0ec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1460113
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/clk_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 45af68ea..b69f74b2 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c | |||
@@ -17,7 +17,6 @@ | |||
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/clk.h> | 19 | #include <linux/clk.h> |
20 | #include <linux/delay.h> /* for mdelay */ | ||
21 | #include <linux/module.h> | 20 | #include <linux/module.h> |
22 | #include <linux/debugfs.h> | 21 | #include <linux/debugfs.h> |
23 | #include <linux/clk/tegra.h> | 22 | #include <linux/clk/tegra.h> |
@@ -26,6 +25,7 @@ | |||
26 | 25 | ||
27 | #include <nvgpu/log.h> | 26 | #include <nvgpu/log.h> |
28 | #include <nvgpu/soc.h> | 27 | #include <nvgpu/soc.h> |
28 | #include <nvgpu/timers.h> | ||
29 | #include <nvgpu/bug.h> | 29 | #include <nvgpu/bug.h> |
30 | 30 | ||
31 | #include <nvgpu/hw/gk20a/hw_trim_gk20a.h> | 31 | #include <nvgpu/hw/gk20a/hw_trim_gk20a.h> |
@@ -223,7 +223,7 @@ static int clk_slide_gpc_pll(struct gk20a *g, u32 n) | |||
223 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); | 223 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); |
224 | coeff = set_field(coeff, trim_sys_gpcpll_coeff_ndiv_m(), | 224 | coeff = set_field(coeff, trim_sys_gpcpll_coeff_ndiv_m(), |
225 | trim_sys_gpcpll_coeff_ndiv_f(n)); | 225 | trim_sys_gpcpll_coeff_ndiv_f(n)); |
226 | udelay(1); | 226 | nvgpu_udelay(1); |
227 | gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff); | 227 | gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff); |
228 | 228 | ||
229 | /* dynamic ramp to new ndiv */ | 229 | /* dynamic ramp to new ndiv */ |
@@ -231,11 +231,11 @@ static int clk_slide_gpc_pll(struct gk20a *g, u32 n) | |||
231 | data = set_field(data, | 231 | data = set_field(data, |
232 | trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(), | 232 | trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(), |
233 | trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f()); | 233 | trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f()); |
234 | udelay(1); | 234 | nvgpu_udelay(1); |
235 | gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data); | 235 | gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data); |
236 | 236 | ||
237 | do { | 237 | do { |
238 | udelay(1); | 238 | nvgpu_udelay(1); |
239 | ramp_timeout--; | 239 | ramp_timeout--; |
240 | data = gk20a_readl( | 240 | data = gk20a_readl( |
241 | g, trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r()); | 241 | g, trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r()); |
@@ -304,7 +304,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, | |||
304 | data = gk20a_readl(g, trim_sys_sel_vco_r()); | 304 | data = gk20a_readl(g, trim_sys_sel_vco_r()); |
305 | data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(), | 305 | data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(), |
306 | trim_sys_sel_vco_gpc2clk_out_bypass_f()); | 306 | trim_sys_sel_vco_gpc2clk_out_bypass_f()); |
307 | udelay(2); | 307 | nvgpu_udelay(2); |
308 | gk20a_writel(g, trim_sys_sel_vco_r(), data); | 308 | gk20a_writel(g, trim_sys_sel_vco_r(), data); |
309 | 309 | ||
310 | /* get out from IDDQ */ | 310 | /* get out from IDDQ */ |
@@ -314,7 +314,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, | |||
314 | trim_sys_gpcpll_cfg_iddq_power_on_v()); | 314 | trim_sys_gpcpll_cfg_iddq_power_on_v()); |
315 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); | 315 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); |
316 | gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 316 | gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
317 | udelay(gpc_pll_params.iddq_exit_delay); | 317 | nvgpu_udelay(gpc_pll_params.iddq_exit_delay); |
318 | } | 318 | } |
319 | 319 | ||
320 | /* disable PLL before changing coefficients */ | 320 | /* disable PLL before changing coefficients */ |
@@ -353,7 +353,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, | |||
353 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 353 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
354 | if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f()) | 354 | if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f()) |
355 | goto pll_locked; | 355 | goto pll_locked; |
356 | udelay(2); | 356 | nvgpu_udelay(2); |
357 | } while (--timeout > 0); | 357 | } while (--timeout > 0); |
358 | 358 | ||
359 | /* PLL is messed up. What can we do here? */ | 359 | /* PLL is messed up. What can we do here? */ |
@@ -372,7 +372,7 @@ pll_locked: | |||
372 | data = gk20a_readl(g, trim_sys_gpc2clk_out_r()); | 372 | data = gk20a_readl(g, trim_sys_gpc2clk_out_r()); |
373 | data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(), | 373 | data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(), |
374 | trim_sys_gpc2clk_out_vcodiv_by1_f()); | 374 | trim_sys_gpc2clk_out_vcodiv_by1_f()); |
375 | udelay(2); | 375 | nvgpu_udelay(2); |
376 | gk20a_writel(g, trim_sys_gpc2clk_out_r(), data); | 376 | gk20a_writel(g, trim_sys_gpc2clk_out_r(), data); |
377 | 377 | ||
378 | /* slide up to target NDIV */ | 378 | /* slide up to target NDIV */ |
@@ -791,10 +791,10 @@ static int monitor_get(void *data, u64 *val) | |||
791 | /* It should take about 8us to finish 100 cycle of 12MHz. | 791 | /* It should take about 8us to finish 100 cycle of 12MHz. |
792 | But longer than 100us delay is required here. */ | 792 | But longer than 100us delay is required here. */ |
793 | gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0)); | 793 | gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0)); |
794 | udelay(2000); | 794 | nvgpu_udelay(2000); |
795 | 795 | ||
796 | count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); | 796 | count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); |
797 | udelay(100); | 797 | nvgpu_udelay(100); |
798 | count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); | 798 | count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); |
799 | freq *= trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2); | 799 | freq *= trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2); |
800 | do_div(freq, ncycle); | 800 | do_div(freq, ncycle); |