From 22426a5452ba943ac48867722fb0927baf66d4ac Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 10 Apr 2017 10:47:02 -0700 Subject: gpu: nvgpu: gk20a: Use new delay APIs Use platform agnostic delay functions instead of Linux kernel APIs. This allows removing dependency to Linux header linux/delay.h. At the same time remove #include lines for other unused Linux headers. JIRA NVGPU-16 Change-Id: I46b9ccb80e0b67efb86ec85676e5a55ff835c0ec Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1460113 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman --- drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/clk_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 45af68ea..b69f74b2 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c @@ -17,7 +17,6 @@ */ #include -#include /* for mdelay */ #include #include #include @@ -26,6 +25,7 @@ #include #include +#include #include #include @@ -223,7 +223,7 @@ static int clk_slide_gpc_pll(struct gk20a *g, u32 n) coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); coeff = set_field(coeff, trim_sys_gpcpll_coeff_ndiv_m(), trim_sys_gpcpll_coeff_ndiv_f(n)); - udelay(1); + nvgpu_udelay(1); gk20a_writel(g, trim_sys_gpcpll_coeff_r(), coeff); /* dynamic ramp to new ndiv */ @@ -231,11 +231,11 @@ static int clk_slide_gpc_pll(struct gk20a *g, u32 n) data = set_field(data, trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(), trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f()); - udelay(1); + nvgpu_udelay(1); gk20a_writel(g, trim_sys_gpcpll_ndiv_slowdown_r(), data); do { - udelay(1); + nvgpu_udelay(1); ramp_timeout--; data = gk20a_readl( g, trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r()); @@ -304,7 +304,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, data = gk20a_readl(g, trim_sys_sel_vco_r()); data = set_field(data, trim_sys_sel_vco_gpc2clk_out_m(), trim_sys_sel_vco_gpc2clk_out_bypass_f()); - udelay(2); + nvgpu_udelay(2); gk20a_writel(g, trim_sys_sel_vco_r(), data); /* get out from IDDQ */ @@ -314,7 +314,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, trim_sys_gpcpll_cfg_iddq_power_on_v()); gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); gk20a_readl(g, trim_sys_gpcpll_cfg_r()); - udelay(gpc_pll_params.iddq_exit_delay); + nvgpu_udelay(gpc_pll_params.iddq_exit_delay); } /* disable PLL before changing coefficients */ @@ -353,7 +353,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f()) goto pll_locked; - udelay(2); + nvgpu_udelay(2); } while (--timeout > 0); /* PLL is messed up. What can we do here? */ @@ -372,7 +372,7 @@ pll_locked: data = gk20a_readl(g, trim_sys_gpc2clk_out_r()); data = set_field(data, trim_sys_gpc2clk_out_vcodiv_m(), trim_sys_gpc2clk_out_vcodiv_by1_f()); - udelay(2); + nvgpu_udelay(2); gk20a_writel(g, trim_sys_gpc2clk_out_r(), data); /* slide up to target NDIV */ @@ -791,10 +791,10 @@ static int monitor_get(void *data, u64 *val) /* It should take about 8us to finish 100 cycle of 12MHz. But longer than 100us delay is required here. */ gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0)); - udelay(2000); + nvgpu_udelay(2000); count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); - udelay(100); + nvgpu_udelay(100); count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); freq *= trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2); do_div(freq, ncycle); -- cgit v1.2.2