diff options
author | Sam Payne <spayne@nvidia.com> | 2015-01-12 17:24:55 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 21:02:35 -0400 |
commit | edaf6188d54683bd955f1dc6673b3bb3ba18367e (patch) | |
tree | 68e95507fb3fed06da3d8a381d113a822d329ed6 /drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |
parent | 3764ce3de36d9b01948a78ec1ecf4ac4371b8e4d (diff) |
gpu: nvgpu: enable ce2 interrupts
enables non-blocking interrupts in ce2 all other
ce2 interrupts are cleared and not handled.
bug 200036089
Change-Id: I9f47b06c677c72ac523019e6a3f70fedd07830a2
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/671783
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/ce2_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c new file mode 100644 index 00000000..75df4ce5 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -0,0 +1,95 @@ | |||
1 | /* | ||
2 | * GK20A Graphics Copy Engine (gr host) | ||
3 | * | ||
4 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along with | ||
16 | * this program; if not, write to the Free Software Foundation, Inc., | ||
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
18 | */ | ||
19 | |||
20 | /*TODO: remove uncecessary */ | ||
21 | #include <linux/delay.h> | ||
22 | #include <linux/slab.h> | ||
23 | #include <linux/scatterlist.h> | ||
24 | #include <trace/events/gk20a.h> | ||
25 | #include <linux/dma-mapping.h> | ||
26 | #include <linux/nvhost.h> | ||
27 | |||
28 | #include "gk20a.h" | ||
29 | #include "debug_gk20a.h" | ||
30 | #include "semaphore_gk20a.h" | ||
31 | #include "hw_ce2_gk20a.h" | ||
32 | #include "hw_pbdma_gk20a.h" | ||
33 | #include "hw_ccsr_gk20a.h" | ||
34 | #include "hw_ram_gk20a.h" | ||
35 | #include "hw_proj_gk20a.h" | ||
36 | #include "hw_top_gk20a.h" | ||
37 | #include "hw_mc_gk20a.h" | ||
38 | #include "hw_gr_gk20a.h" | ||
39 | |||
40 | static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
41 | { | ||
42 | gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); | ||
43 | |||
44 | /* wake theads waiting in this channel */ | ||
45 | gk20a_channel_semaphore_wakeup(g); | ||
46 | return ce2_intr_status_nonblockpipe_pending_f(); | ||
47 | } | ||
48 | |||
49 | static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
50 | { | ||
51 | gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); | ||
52 | |||
53 | return ce2_intr_status_blockpipe_pending_f(); | ||
54 | } | ||
55 | |||
56 | static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) | ||
57 | { | ||
58 | gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n"); | ||
59 | |||
60 | return ce2_intr_status_launcherr_pending_f(); | ||
61 | } | ||
62 | |||
63 | void gk20a_ce2_isr(struct gk20a *g) | ||
64 | { | ||
65 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); | ||
66 | u32 clear_intr = 0; | ||
67 | |||
68 | gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); | ||
69 | |||
70 | /* clear blocking interrupts: they exibit broken behavior */ | ||
71 | if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) | ||
72 | clear_intr |= ce2_blockpipe_isr(g, ce2_intr); | ||
73 | |||
74 | if (ce2_intr & ce2_intr_status_launcherr_pending_f()) | ||
75 | clear_intr |= ce2_launcherr_isr(g, ce2_intr); | ||
76 | |||
77 | gk20a_writel(g, ce2_intr_status_r(), clear_intr); | ||
78 | return; | ||
79 | } | ||
80 | |||
81 | void gk20a_ce2_nonstall_isr(struct gk20a *g) | ||
82 | { | ||
83 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); | ||
84 | u32 clear_intr = 0; | ||
85 | |||
86 | gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); | ||
87 | |||
88 | if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) | ||
89 | clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); | ||
90 | |||
91 | gk20a_writel(g, ce2_intr_status_r(), clear_intr); | ||
92 | |||
93 | return; | ||
94 | } | ||
95 | |||