diff options
author | David Nieto <dmartineznie@nvidia.com> | 2017-02-06 18:44:55 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-14 14:46:38 -0400 |
commit | 403874fa75dbb00e974a8d0f88b6e92be01ba42e (patch) | |
tree | 0492e82ded3c4ce7ee4438b29bcadc2db9472279 /drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |
parent | 4deb494ad114088f5253d02d9ec31f9aaeb2778a (diff) |
gpu: nvgpu: refactor interrupt handling
JIRA: EVLR-1004
(*) Refactor the non-stalling interrupt path to execute clear on the
top half, so on dGPU case processing of stalling interrupts does not
block non-stalling one.
(*) Use a worker thread to do semaphore wakeups and allow batching of
the non-stalling operations.
(*) Fix a bug where some gpus will not properly track the completion
of interrupts, preventing safe driver unloads
Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1312796
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Navneet Kumar <navneetk@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a/ce2_gk20a.c')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index db1ac539..3fed937e 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -76,8 +76,9 @@ void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
76 | return; | 76 | return; |
77 | } | 77 | } |
78 | 78 | ||
79 | void gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | 79 | int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) |
80 | { | 80 | { |
81 | int ops = 0; | ||
81 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); | 82 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); |
82 | 83 | ||
83 | gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); | 84 | gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); |
@@ -85,12 +86,10 @@ void gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
85 | if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) { | 86 | if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) { |
86 | gk20a_writel(g, ce2_intr_status_r(), | 87 | gk20a_writel(g, ce2_intr_status_r(), |
87 | ce2_nonblockpipe_isr(g, ce2_intr)); | 88 | ce2_nonblockpipe_isr(g, ce2_intr)); |
88 | 89 | ops |= (gk20a_nonstall_ops_wakeup_semaphore | | |
89 | /* wake threads waiting in this channel */ | 90 | gk20a_nonstall_ops_post_events); |
90 | gk20a_channel_semaphore_wakeup(g, true); | ||
91 | } | 91 | } |
92 | 92 | return ops; | |
93 | return; | ||
94 | } | 93 | } |
95 | void gk20a_init_ce2(struct gpu_ops *gops) | 94 | void gk20a_init_ce2(struct gpu_ops *gops) |
96 | { | 95 | { |