From 403874fa75dbb00e974a8d0f88b6e92be01ba42e Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 6 Feb 2017 15:44:55 -0800 Subject: gpu: nvgpu: refactor interrupt handling JIRA: EVLR-1004 (*) Refactor the non-stalling interrupt path to execute clear on the top half, so on dGPU case processing of stalling interrupts does not block non-stalling one. (*) Use a worker thread to do semaphore wakeups and allow batching of the non-stalling operations. (*) Fix a bug where some gpus will not properly track the completion of interrupts, preventing safe driver unloads Change-Id: Icc90a3acba544c97ec6a9285ab235d337ab9eefa Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1312796 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Lakshmanan M Reviewed-by: Terje Bergstrom Reviewed-by: Navneet Kumar --- drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/ce2_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index db1ac539..3fed937e 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c @@ -76,8 +76,9 @@ void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base) return; } -void gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) { + int ops = 0; u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); @@ -85,12 +86,10 @@ void gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) { gk20a_writel(g, ce2_intr_status_r(), ce2_nonblockpipe_isr(g, ce2_intr)); - - /* wake threads waiting in this channel */ - gk20a_channel_semaphore_wakeup(g, true); + ops |= (gk20a_nonstall_ops_wakeup_semaphore | + gk20a_nonstall_ops_post_events); } - - return; + return ops; } void gk20a_init_ce2(struct gpu_ops *gops) { -- cgit v1.2.2