gpu: nvgpu: Move MC HAL to common

Move implementation of MC HAL to common/mc. Also bump gk20a
implementation to gm20b.

gk20a_mc_boot_0 was used via a HAL, but we have only one possible
implementation. It also has to be anyway called directly to detect
which HALs to assign, so make it a true common function.

mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c
so move it there.

JIRA NVGPU-954

Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813519
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

9 files changed, 919 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/common/mc/mc.c b/drivers/gpu/nvgpu/common/mc/mc.c
new file mode 100644
index 00000000..77416ef9
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/mc.c
@@ -0,0 +1,54 @@
+/*
+ * GK20A Master Control
+ *
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/io.h>
+#include <nvgpu/mc.h>
+
+#include "gk20a/gk20a.h"
+
+#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
+
+u32 nvgpu_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
+{
+        u32 val = __nvgpu_readl(g, mc_boot_0_r());
+
+        if (val != 0xffffffffU) {
+
+                if (arch != NULL) {
+                        *arch = mc_boot_0_architecture_v(val) <<
+                                NVGPU_GPU_ARCHITECTURE_SHIFT;
+                }
+
+                if (impl != NULL) {
+                        *impl = mc_boot_0_implementation_v(val);
+                }
+
+                if (rev != NULL) {
+                        *rev = (mc_boot_0_major_revision_v(val) << 4) |
+                                mc_boot_0_minor_revision_v(val);
+                }
+        }
+
+        return val;
+}
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.c b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c
new file mode 100644
index 00000000..88666b1d
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.c
@@ -0,0 +1,294 @@
+/*
+ * GK20A Master Control
+ *
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/timers.h>
+#include <nvgpu/atomic.h>
+#include <nvgpu/unit.h>
+#include <nvgpu/io.h>
+#include <nvgpu/mc.h>
+
+#include "gk20a/gk20a.h"
+#include "mc_gm20b.h"
+
+#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
+
+void gm20b_mc_isr_stall(struct gk20a *g)
+{
+        u32 mc_intr_0;
+        u32 engine_id_idx;
+        u32 active_engine_id = 0;
+        u32 engine_enum = ENGINE_INVAL_GK20A;
+
+        mc_intr_0 = g->ops.mc.intr_stall(g);
+
+        nvgpu_log(g, gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
+
+        for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
+                active_engine_id = g->fifo.active_engines_list[engine_id_idx];
+
+                if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) {
+                        engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
+                        /* GR Engine */
+                        if (engine_enum == ENGINE_GR_GK20A) {
+                                gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
+                        }
+
+                        /* CE Engine */
+                        if (((engine_enum == ENGINE_GRCE_GK20A) ||
+                                (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
+                                (g->ops.ce2.isr_stall != NULL)) {
+                                        g->ops.ce2.isr_stall(g,
+                                        g->fifo.engine_info[active_engine_id].inst_id,
+                                        g->fifo.engine_info[active_engine_id].pri_base);
+                        }
+                }
+        }
+        if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) {
+                gk20a_fifo_isr(g);
+        }
+        if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) {
+                g->ops.pmu.pmu_isr(g);
+        }
+        if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
+                g->ops.priv_ring.isr(g);
+        }
+        if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) {
+                g->ops.ltc.isr(g);
+        }
+        if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
+                g->ops.bus.isr(g);
+        }
+}
+
+u32 gm20b_mc_isr_nonstall(struct gk20a *g)
+{
+        u32 ops = 0;
+        u32 mc_intr_1;
+        u32 engine_id_idx;
+        u32 active_engine_id = 0;
+        u32 engine_enum = ENGINE_INVAL_GK20A;
+
+        mc_intr_1 = g->ops.mc.intr_nonstall(g);
+
+        if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1) != 0U) {
+                ops |= gk20a_fifo_nonstall_isr(g);
+        }
+
+        for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines;
+                                                        engine_id_idx++) {
+                struct fifo_engine_info_gk20a *engine_info;
+
+                active_engine_id = g->fifo.active_engines_list[engine_id_idx];
+                engine_info = &g->fifo.engine_info[active_engine_id];
+
+                if ((mc_intr_1 & engine_info->intr_mask) != 0U) {
+                        engine_enum = engine_info->engine_enum;
+                        /* GR Engine */
+                        if (engine_enum == ENGINE_GR_GK20A) {
+                                ops |= gk20a_gr_nonstall_isr(g);
+                        }
+                        /* CE Engine */
+                        if (((engine_enum == ENGINE_GRCE_GK20A) ||
+                             (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
+                              (g->ops.ce2.isr_nonstall != NULL)) {
+                                ops |= g->ops.ce2.isr_nonstall(g,
+                                        engine_info->inst_id,
+                                        engine_info->pri_base);
+                        }
+                }
+        }
+
+        return ops;
+}
+
+void gm20b_mc_intr_mask(struct gk20a *g)
+{
+        nvgpu_writel(g, mc_intr_en_0_r(),
+                mc_intr_en_0_inta_disabled_f());
+        nvgpu_writel(g, mc_intr_en_1_r(),
+                mc_intr_en_1_inta_disabled_f());
+}
+
+void gm20b_mc_intr_enable(struct gk20a *g)
+{
+        u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
+
+        gk20a_writel(g, mc_intr_mask_1_r(),
+                     mc_intr_pfifo_pending_f()
+                     | eng_intr_mask);
+        gk20a_writel(g, mc_intr_en_1_r(),
+                mc_intr_en_1_inta_hardware_f());
+
+        gk20a_writel(g, mc_intr_mask_0_r(),
+                     mc_intr_pfifo_pending_f()
+                     | mc_intr_priv_ring_pending_f()
+                     | mc_intr_ltc_pending_f()
+                     | mc_intr_pbus_pending_f()
+                     | eng_intr_mask);
+        gk20a_writel(g, mc_intr_en_0_r(),
+                mc_intr_en_0_inta_hardware_f());
+}
+
+void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable,
+                bool is_stalling, u32 mask)
+{
+        u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() :
+                                        mc_intr_mask_1_r());
+
+        if (enable) {
+                gk20a_writel(g, mask_reg,
+                        gk20a_readl(g, mask_reg) |
+                        mask);
+        } else {
+                gk20a_writel(g, mask_reg,
+                        gk20a_readl(g, mask_reg) &
+                        ~mask);
+        }
+}
+
+void gm20b_mc_intr_stall_pause(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_0_r(),
+                mc_intr_en_0_inta_disabled_f());
+
+        /* flush previous write */
+        (void) gk20a_readl(g, mc_intr_en_0_r());
+}
+
+void gm20b_mc_intr_stall_resume(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_0_r(),
+                mc_intr_en_0_inta_hardware_f());
+
+        /* flush previous write */
+        (void) gk20a_readl(g, mc_intr_en_0_r());
+}
+
+void gm20b_mc_intr_nonstall_pause(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_1_r(),
+                mc_intr_en_0_inta_disabled_f());
+
+        /* flush previous write */
+        (void) gk20a_readl(g, mc_intr_en_1_r());
+}
+
+void gm20b_mc_intr_nonstall_resume(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_1_r(),
+                mc_intr_en_0_inta_hardware_f());
+
+        /* flush previous write */
+        (void) gk20a_readl(g, mc_intr_en_1_r());
+}
+
+u32 gm20b_mc_intr_stall(struct gk20a *g)
+{
+        return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
+}
+
+u32 gm20b_mc_intr_nonstall(struct gk20a *g)
+{
+        return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
+}
+
+void gm20b_mc_disable(struct gk20a *g, u32 units)
+{
+        u32 pmc;
+
+        nvgpu_log(g, gpu_dbg_info, "pmc disable: %08x\n", units);
+
+        nvgpu_spinlock_acquire(&g->mc_enable_lock);
+        pmc = gk20a_readl(g, mc_enable_r());
+        pmc &= ~units;
+        gk20a_writel(g, mc_enable_r(), pmc);
+        nvgpu_spinlock_release(&g->mc_enable_lock);
+}
+
+void gm20b_mc_enable(struct gk20a *g, u32 units)
+{
+        u32 pmc;
+
+        nvgpu_log(g, gpu_dbg_info, "pmc enable: %08x\n", units);
+
+        nvgpu_spinlock_acquire(&g->mc_enable_lock);
+        pmc = gk20a_readl(g, mc_enable_r());
+        pmc |= units;
+        gk20a_writel(g, mc_enable_r(), pmc);
+        pmc = gk20a_readl(g, mc_enable_r());
+        nvgpu_spinlock_release(&g->mc_enable_lock);
+
+        nvgpu_udelay(20);
+}
+
+void gm20b_mc_reset(struct gk20a *g, u32 units)
+{
+        g->ops.mc.disable(g, units);
+        if ((units & gk20a_fifo_get_all_ce_engine_reset_mask(g)) != 0U) {
+                nvgpu_udelay(500);
+        } else {
+                nvgpu_udelay(20);
+        }
+        g->ops.mc.enable(g, units);
+}
+
+bool gm20b_mc_is_intr1_pending(struct gk20a *g,
+                               enum nvgpu_unit unit, u32 mc_intr_1)
+{
+        u32 mask = 0U;
+        bool is_pending;
+
+        switch (unit) {
+        case NVGPU_UNIT_FIFO:
+                mask = mc_intr_pfifo_pending_f();
+                break;
+        default:
+                break;
+        }
+
+        if (mask == 0U) {
+                nvgpu_err(g, "unknown unit %d", unit);
+                is_pending = false;
+        } else {
+                is_pending = ((mc_intr_1 & mask) != 0U) ? true : false;
+        }
+
+        return is_pending;
+}
+
+void gm20b_mc_log_pending_intrs(struct gk20a *g)
+{
+        u32 intr;
+
+        intr = g->ops.mc.intr_stall(g);
+        if (intr != 0U) {
+                nvgpu_info(g, "Pending stall intr0=0x%08x", intr);
+        }
+
+        intr = g->ops.mc.intr_nonstall(g);
+        if (intr != 0U) {
+                nvgpu_info(g, "Pending nonstall intr1=0x%08x", intr);
+        }
+}
+
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gm20b.h b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h
new file mode 100644
index 00000000..6700a48c
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/mc_gm20b.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_MC_GM20B_H
+#define NVGPU_MC_GM20B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+enum nvgpu_unit;
+
+void gm20b_mc_intr_mask(struct gk20a *g);
+void gm20b_mc_intr_enable(struct gk20a *g);
+void gm20b_mc_intr_unit_config(struct gk20a *g, bool enable,
+                bool is_stalling, u32 mask);
+void gm20b_mc_isr_stall(struct gk20a *g);
+u32 gm20b_mc_intr_stall(struct gk20a *g);
+void gm20b_mc_intr_stall_pause(struct gk20a *g);
+void gm20b_mc_intr_stall_resume(struct gk20a *g);
+u32 gm20b_mc_intr_nonstall(struct gk20a *g);
+u32 gm20b_mc_isr_nonstall(struct gk20a *g);
+void gm20b_mc_intr_nonstall_pause(struct gk20a *g);
+void gm20b_mc_intr_nonstall_resume(struct gk20a *g);
+void gm20b_mc_enable(struct gk20a *g, u32 units);
+void gm20b_mc_disable(struct gk20a *g, u32 units);
+void gm20b_mc_reset(struct gk20a *g, u32 units);
+bool gm20b_mc_is_intr1_pending(struct gk20a *g,
+                enum nvgpu_unit unit, u32 mc_intr_1);
+void gm20b_mc_log_pending_intrs(struct gk20a *g);
+void gm20b_mc_handle_intr_nonstall(struct gk20a *g, u32 ops);
+
+#endif /* NVGPU_MC_GM20B_H */
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c
new file mode 100644
index 00000000..a0f26dd3
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c
@@ -0,0 +1,224 @@
+/*
+ * GP10B master
+ *
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include "gk20a/gk20a.h"
+#include <nvgpu/io.h>
+#include <nvgpu/mc.h>
+
+#include "mc_gp10b.h"
+
+#include <nvgpu/atomic.h>
+#include <nvgpu/unit.h>
+
+#include <nvgpu/hw/gp10b/hw_mc_gp10b.h>
+
+#define MAX_MC_INTR_REGS        2U
+
+void mc_gp10b_intr_mask(struct gk20a *g)
+{
+        nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
+                                0xffffffffU);
+
+        nvgpu_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
+                                0xffffffffU);
+}
+
+void mc_gp10b_intr_enable(struct gk20a *g)
+{
+        u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
+
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
+                                0xffffffffU);
+        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
+                                mc_intr_pfifo_pending_f() |
+                                 mc_intr_priv_ring_pending_f() |
+                                 mc_intr_pbus_pending_f() |
+                                 mc_intr_ltc_pending_f() |
+                                 mc_intr_replayable_fault_pending_f() |
+                                 eng_intr_mask;
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
+
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
+                                0xffffffffU);
+        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
+                                mc_intr_pfifo_pending_f() |
+                                 eng_intr_mask;
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
+}
+
+void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
+                bool is_stalling, u32 mask)
+{
+        u32 intr_index = 0;
+        u32 reg = 0;
+
+        intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING :
+                        NVGPU_MC_INTR_NONSTALLING);
+        if (enable) {
+                reg = mc_intr_en_set_r(intr_index);
+                g->mc_intr_mask_restore[intr_index] |= mask;
+
+        } else {
+                reg = mc_intr_en_clear_r(intr_index);
+                g->mc_intr_mask_restore[intr_index] &= ~mask;
+        }
+
+        gk20a_writel(g, reg, mask);
+}
+
+void mc_gp10b_isr_stall(struct gk20a *g)
+{
+        u32 mc_intr_0;
+
+        u32 engine_id_idx;
+        u32 active_engine_id = 0;
+        u32 engine_enum = ENGINE_INVAL_GK20A;
+
+        mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
+
+        nvgpu_log(g, gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0);
+
+        for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) {
+                active_engine_id = g->fifo.active_engines_list[engine_id_idx];
+
+                if ((mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) != 0U) {
+                        engine_enum = g->fifo.engine_info[active_engine_id].engine_enum;
+                        /* GR Engine */
+                        if (engine_enum == ENGINE_GR_GK20A) {
+                                gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
+                        }
+
+                        /* CE Engine */
+                        if (((engine_enum == ENGINE_GRCE_GK20A) ||
+                                (engine_enum == ENGINE_ASYNC_CE_GK20A)) &&
+                                (g->ops.ce2.isr_stall != NULL)) {
+                                        g->ops.ce2.isr_stall(g,
+                                        g->fifo.engine_info[active_engine_id].inst_id,
+                                        g->fifo.engine_info[active_engine_id].pri_base);
+                        }
+                }
+        }
+        if ((g->ops.mc.is_intr_hub_pending != NULL) &&
+                 g->ops.mc.is_intr_hub_pending(g, mc_intr_0)) {
+                g->ops.fb.hub_isr(g);
+        }
+        if ((mc_intr_0 & mc_intr_pfifo_pending_f()) != 0U) {
+                gk20a_fifo_isr(g);
+        }
+        if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) {
+                g->ops.pmu.pmu_isr(g);
+        }
+        if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) {
+                g->ops.priv_ring.isr(g);
+        }
+        if ((mc_intr_0 & mc_intr_ltc_pending_f()) != 0U) {
+                g->ops.ltc.isr(g);
+        }
+        if ((mc_intr_0 & mc_intr_pbus_pending_f()) != 0U) {
+                g->ops.bus.isr(g);
+        }
+        if ((g->ops.mc.is_intr_nvlink_pending != NULL) &&
+                        g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) {
+                g->ops.nvlink.isr(g);
+        }
+        if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.fb.fbpa_isr) {
+                g->ops.fb.fbpa_isr(g);
+        }
+
+        nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0);
+
+}
+
+u32 mc_gp10b_intr_stall(struct gk20a *g)
+{
+        return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_STALLING));
+}
+
+void mc_gp10b_intr_stall_pause(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), 0xffffffffU);
+}
+
+void mc_gp10b_intr_stall_resume(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
+}
+
+u32 mc_gp10b_intr_nonstall(struct gk20a *g)
+{
+        return gk20a_readl(g, mc_intr_r(NVGPU_MC_INTR_NONSTALLING));
+}
+
+void mc_gp10b_intr_nonstall_pause(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
+                     0xffffffffU);
+}
+
+void mc_gp10b_intr_nonstall_resume(struct gk20a *g)
+{
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
+}
+
+bool mc_gp10b_is_intr1_pending(struct gk20a *g,
+                                      enum nvgpu_unit unit, u32 mc_intr_1)
+{
+        u32 mask = 0;
+        bool is_pending;
+
+        switch (unit) {
+        case NVGPU_UNIT_FIFO:
+                mask = mc_intr_pfifo_pending_f();
+                break;
+        default:
+                break;
+        }
+
+        if (mask == 0U) {
+                nvgpu_err(g, "unknown unit %d", unit);
+                is_pending = false;
+        } else {
+                is_pending = ((mc_intr_1 & mask) != 0U) ? true : false;
+        }
+
+        return is_pending;
+}
+
+void mc_gp10b_log_pending_intrs(struct gk20a *g)
+{
+        u32 i, intr;
+
+        for (i = 0; i < MAX_MC_INTR_REGS; i++) {
+                intr = nvgpu_readl(g, mc_intr_r(i));
+                if (intr == 0U) {
+                        continue;
+                }
+                nvgpu_info(g, "Pending intr%d=0x%08x", i, intr);
+        }
+
+}
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.h b/drivers/gpu/nvgpu/common/mc/mc_gp10b.h
new file mode 100644
index 00000000..ee3c0c3b
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef MC_GP10B_H
+#define MC_GP10B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+enum nvgpu_unit;
+
+void mc_gp10b_intr_mask(struct gk20a *g);
+void mc_gp10b_intr_enable(struct gk20a *g);
+void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable,
+                bool is_stalling, u32 mask);
+void mc_gp10b_isr_stall(struct gk20a *g);
+bool mc_gp10b_is_intr1_pending(struct gk20a *g,
+                                      enum nvgpu_unit unit, u32 mc_intr_1);
+
+void mc_gp10b_log_pending_intrs(struct gk20a *g);
+u32 mc_gp10b_intr_stall(struct gk20a *g);
+void mc_gp10b_intr_stall_pause(struct gk20a *g);
+void mc_gp10b_intr_stall_resume(struct gk20a *g);
+u32 mc_gp10b_intr_nonstall(struct gk20a *g);
+void mc_gp10b_intr_nonstall_pause(struct gk20a *g);
+void mc_gp10b_intr_nonstall_resume(struct gk20a *g);
+
+#endif
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.c b/drivers/gpu/nvgpu/common/mc/mc_gv100.c
new file mode 100644
index 00000000..28c03434
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.c
@@ -0,0 +1,91 @@
+/*
+ * GV100 master
+ *
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/io.h>
+#include <nvgpu/mc.h>
+
+#include "gk20a/gk20a.h"
+
+#include "mc_gp10b.h"
+#include "mc_gv100.h"
+
+#include <nvgpu/hw/gv100/hw_mc_gv100.h>
+
+void mc_gv100_intr_enable(struct gk20a *g)
+{
+        u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
+
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
+                                0xffffffffU);
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
+                                0xffffffffU);
+        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
+                                mc_intr_pfifo_pending_f() |
+                                mc_intr_hub_pending_f() |
+                                mc_intr_priv_ring_pending_f() |
+                                mc_intr_pbus_pending_f() |
+                                mc_intr_ltc_pending_f() |
+                                mc_intr_nvlink_pending_f() |
+                                eng_intr_mask;
+
+        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
+                                mc_intr_pfifo_pending_f()
+                             | eng_intr_mask;
+
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
+
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
+
+}
+
+bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0)
+{
+        return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false);
+}
+
+bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
+                        u32 *eng_intr_pending)
+{
+        u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
+        u32 stall_intr, eng_intr_mask;
+
+        eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
+        *eng_intr_pending = mc_intr_0 & eng_intr_mask;
+
+        stall_intr = mc_intr_pfifo_pending_f() |
+                        mc_intr_hub_pending_f() |
+                        mc_intr_priv_ring_pending_f() |
+                        mc_intr_pbus_pending_f() |
+                        mc_intr_ltc_pending_f() |
+                        mc_intr_nvlink_pending_f();
+
+        nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
+                "mc_intr_0 = 0x%08x, eng_intr = 0x%08x",
+                mc_intr_0 & stall_intr, *eng_intr_pending);
+
+        return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
+}
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.h b/drivers/gpu/nvgpu/common/mc/mc_gv100.h
new file mode 100644
index 00000000..c0a16ad9
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef MC_GV100_H
+#define MC_GV100_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void mc_gv100_intr_enable(struct gk20a *g);
+bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0);
+bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
+                        u32 *eng_intr_pending);
+#endif
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv11b.c b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c
new file mode 100644
index 00000000..fa4d4bfb
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/mc_gv11b.c
@@ -0,0 +1,90 @@
+/*
+ * GV11B master
+ *
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/types.h>
+#include <nvgpu/io.h>
+#include <nvgpu/mc.h>
+
+#include "gk20a/gk20a.h"
+
+#include "mc_gp10b.h"
+#include "mc_gv11b.h"
+
+#include <nvgpu/hw/gv11b/hw_mc_gv11b.h>
+
+void mc_gv11b_intr_enable(struct gk20a *g)
+{
+        u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
+
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING),
+                                0xffffffffU);
+        gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
+                                0xffffffffU);
+
+        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
+                                mc_intr_pfifo_pending_f() |
+                                mc_intr_hub_pending_f() |
+                                mc_intr_priv_ring_pending_f() |
+                                mc_intr_pbus_pending_f() |
+                                mc_intr_ltc_pending_f() |
+                                eng_intr_mask;
+
+        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] =
+                                mc_intr_pfifo_pending_f()
+                             | eng_intr_mask;
+
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
+
+        gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING),
+                        g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]);
+
+}
+
+bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0)
+{
+        return (((mc_intr_0 & mc_intr_hub_pending_f()) != 0U) ? true : false);
+}
+
+bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
+                        u32 *eng_intr_pending)
+{
+        u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0));
+        u32 stall_intr, eng_intr_mask;
+
+        eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id);
+        *eng_intr_pending = mc_intr_0 & eng_intr_mask;
+
+        stall_intr = mc_intr_pfifo_pending_f() |
+                        mc_intr_hub_pending_f() |
+                        mc_intr_priv_ring_pending_f() |
+                        mc_intr_pbus_pending_f() |
+                        mc_intr_ltc_pending_f();
+
+        nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr,
+                "mc_intr_0 = 0x%08x, eng_intr = 0x%08x",
+                mc_intr_0 & stall_intr, *eng_intr_pending);
+
+        return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U;
+}
diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv11b.h b/drivers/gpu/nvgpu/common/mc/mc_gv11b.h
new file mode 100644
index 00000000..48eba744
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/mc/mc_gv11b.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef MC_GV11B_H
+#define MC_GV11B_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+
+void mc_gv11b_intr_enable(struct gk20a *g);
+bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
+bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id,
+                        u32 *eng_intr_pending);
+#endif