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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-05-24 16:46:53 -0400
committerTejal Kudav <tkudav@nvidia.com>2018-06-14 09:44:07 -0400
commitf9a2f449a5f4dd62fcfb1701d69dc40f97a827ff (patch)
tree44cfc3aa4ff94ab23ffa5f3363fb8536848053ea /drivers/gpu/nvgpu/common/bus
parentdbb8792baf2142626728abf909fb201144b9b56a (diff)
gpu: nvgpu: Remove direct MC and GR deps from bus
bus_gk20a.c had some debug dump references to MC and GR registers. The dumps have not been very useful, so instead of refactoring the code just remove the dumps. JIRA NVGPU-588 Change-Id: Id974731716d058ef4a3fe77240c11b1c53db169c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730891 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/bus')
-rw-r--r--drivers/gpu/nvgpu/common/bus/bus_gk20a.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
index a2c6a3d7..d173123d 100644
--- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
+++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
@@ -28,8 +28,6 @@
28#include "bus_gk20a.h" 28#include "bus_gk20a.h"
29 29
30#include <nvgpu/hw/gk20a/hw_bus_gk20a.h> 30#include <nvgpu/hw/gk20a/hw_bus_gk20a.h>
31#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
32#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
33#include <nvgpu/hw/gk20a/hw_timer_gk20a.h> 31#include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
34 32
35void gk20a_bus_init_hw(struct gk20a *g) 33void gk20a_bus_init_hw(struct gk20a *g)
@@ -70,9 +68,6 @@ void gk20a_bus_isr(struct gk20a *g)
70 bus_intr_0_pri_fecserr_m() | 68 bus_intr_0_pri_fecserr_m() |
71 bus_intr_0_pri_timeout_m())) { 69 bus_intr_0_pri_timeout_m())) {
72 70
73 nvgpu_log(g, gpu_dbg_intr, "pmc_enable : 0x%x",
74 gk20a_readl(g, mc_enable_r()));
75
76 save0 = gk20a_readl(g, timer_pri_timeout_save_0_r()); 71 save0 = gk20a_readl(g, timer_pri_timeout_save_0_r());
77 if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) { 72 if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) {
78 /* 73 /*
@@ -99,11 +94,6 @@ void gk20a_bus_isr(struct gk20a *g)
99 if (g->ops.priv_ring.decode_error_code) 94 if (g->ops.priv_ring.decode_error_code)
100 g->ops.priv_ring.decode_error_code(g, 95 g->ops.priv_ring.decode_error_code(g,
101 fecs_errcode); 96 fecs_errcode);
102
103 if ((fecs_errcode & 0xffffff00) == 0xbadf1300)
104 nvgpu_err(g, "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: "
105 "0x%08x",
106 gk20a_readl(g, gr_gpc0_fs_gpc_r()));
107 } 97 }
108 98
109 } else { 99 } else {