From f9a2f449a5f4dd62fcfb1701d69dc40f97a827ff Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 24 May 2018 13:46:53 -0700 Subject: gpu: nvgpu: Remove direct MC and GR deps from bus bus_gk20a.c had some debug dump references to MC and GR registers. The dumps have not been very useful, so instead of refactoring the code just remove the dumps. JIRA NVGPU-588 Change-Id: Id974731716d058ef4a3fe77240c11b1c53db169c Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1730891 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/bus/bus_gk20a.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'drivers/gpu/nvgpu/common/bus') diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c index a2c6a3d7..d173123d 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c @@ -28,8 +28,6 @@ #include "bus_gk20a.h" #include -#include -#include #include void gk20a_bus_init_hw(struct gk20a *g) @@ -70,9 +68,6 @@ void gk20a_bus_isr(struct gk20a *g) bus_intr_0_pri_fecserr_m() | bus_intr_0_pri_timeout_m())) { - nvgpu_log(g, gpu_dbg_intr, "pmc_enable : 0x%x", - gk20a_readl(g, mc_enable_r())); - save0 = gk20a_readl(g, timer_pri_timeout_save_0_r()); if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) { /* @@ -99,11 +94,6 @@ void gk20a_bus_isr(struct gk20a *g) if (g->ops.priv_ring.decode_error_code) g->ops.priv_ring.decode_error_code(g, fecs_errcode); - - if ((fecs_errcode & 0xffffff00) == 0xbadf1300) - nvgpu_err(g, "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: " - "0x%08x", - gk20a_readl(g, gr_gpc0_fs_gpc_r())); } } else { -- cgit v1.2.2