diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-05-24 18:25:41 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:07 -0400 |
commit | d71d38087ded679f60714dae3a859523a19df04f (patch) | |
tree | 61439d294705ef91ce08ae4c02d4921eec943283 /drivers/gpu/nvgpu/common/bus | |
parent | 5215d65c25b5e76c19d9d12b03c52f69e2d40227 (diff) |
gpu: nvgpu: Separate timer from bus
Code touching timer registers was combined with bus code. They're two
logically separate register spaces, so separate the code accordingly.
JIRA NVGPU-588
Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730893
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/bus')
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus.c | 51 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gk20a.c | 72 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gm20b.h | 4 |
5 files changed, 4 insertions, 128 deletions
diff --git a/drivers/gpu/nvgpu/common/bus/bus.c b/drivers/gpu/nvgpu/common/bus/bus.c deleted file mode 100644 index 3889512a..00000000 --- a/drivers/gpu/nvgpu/common/bus/bus.c +++ /dev/null | |||
@@ -1,51 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/bus.h> | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | |||
27 | int nvgpu_get_timestamps_zipper(struct gk20a *g, | ||
28 | u32 source_id, u32 count, | ||
29 | struct nvgpu_cpu_time_correlation_sample *samples) | ||
30 | { | ||
31 | int err = 0; | ||
32 | unsigned int i = 0; | ||
33 | |||
34 | if (gk20a_busy(g)) { | ||
35 | nvgpu_err(g, "GPU not powered on\n"); | ||
36 | err = -EINVAL; | ||
37 | goto end; | ||
38 | } | ||
39 | |||
40 | for (i = 0; i < count; i++) { | ||
41 | err = g->ops.bus.read_ptimer(g, &samples[i].gpu_timestamp); | ||
42 | if (err) | ||
43 | return err; | ||
44 | |||
45 | samples[i].cpu_timestamp = nvgpu_hr_timestamp(); | ||
46 | } | ||
47 | |||
48 | end: | ||
49 | gk20a_idle(g); | ||
50 | return err; | ||
51 | } | ||
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c index 9f0446c6..532fc9c6 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c | |||
@@ -28,7 +28,6 @@ | |||
28 | #include "bus_gk20a.h" | 28 | #include "bus_gk20a.h" |
29 | 29 | ||
30 | #include <nvgpu/hw/gk20a/hw_bus_gk20a.h> | 30 | #include <nvgpu/hw/gk20a/hw_bus_gk20a.h> |
31 | #include <nvgpu/hw/gk20a/hw_timer_gk20a.h> | ||
32 | 31 | ||
33 | void gk20a_bus_init_hw(struct gk20a *g) | 32 | void gk20a_bus_init_hw(struct gk20a *g) |
34 | { | 33 | { |
@@ -45,7 +44,7 @@ void gk20a_bus_init_hw(struct gk20a *g) | |||
45 | 44 | ||
46 | void gk20a_bus_isr(struct gk20a *g) | 45 | void gk20a_bus_isr(struct gk20a *g) |
47 | { | 46 | { |
48 | u32 val, save0, save1, fecs_errcode = 0; | 47 | u32 val; |
49 | 48 | ||
50 | val = gk20a_readl(g, bus_intr_0_r()); | 49 | val = gk20a_readl(g, bus_intr_0_r()); |
51 | 50 | ||
@@ -53,80 +52,13 @@ void gk20a_bus_isr(struct gk20a *g) | |||
53 | bus_intr_0_pri_fecserr_m() | | 52 | bus_intr_0_pri_fecserr_m() | |
54 | bus_intr_0_pri_timeout_m())) { | 53 | bus_intr_0_pri_timeout_m())) { |
55 | 54 | ||
56 | save0 = gk20a_readl(g, timer_pri_timeout_save_0_r()); | 55 | g->ops.ptimer.isr(g); |
57 | if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) { | ||
58 | /* | ||
59 | * write & addr fields in timeout_save0 | ||
60 | * might not be reliable | ||
61 | */ | ||
62 | fecs_errcode = gk20a_readl(g, | ||
63 | timer_pri_timeout_fecs_errcode_r()); | ||
64 | } | ||
65 | |||
66 | save1 = gk20a_readl(g, timer_pri_timeout_save_1_r()); | ||
67 | nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x ADR 0x%08x " | ||
68 | "%s DATA 0x%08x ", | ||
69 | val, | ||
70 | timer_pri_timeout_save_0_addr_v(save0) << 2, | ||
71 | timer_pri_timeout_save_0_write_v(save0) ? | ||
72 | "WRITE" : "READ", save1); | ||
73 | |||
74 | gk20a_writel(g, timer_pri_timeout_save_0_r(), 0); | ||
75 | gk20a_writel(g, timer_pri_timeout_save_1_r(), 0); | ||
76 | |||
77 | if (fecs_errcode) { | ||
78 | nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode); | ||
79 | if (g->ops.priv_ring.decode_error_code) | ||
80 | g->ops.priv_ring.decode_error_code(g, | ||
81 | fecs_errcode); | ||
82 | } | ||
83 | |||
84 | } else { | 56 | } else { |
85 | nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val); | 57 | nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val); |
86 | } | 58 | } |
87 | gk20a_writel(g, bus_intr_0_r(), val); | 59 | gk20a_writel(g, bus_intr_0_r(), val); |
88 | } | 60 | } |
89 | 61 | ||
90 | int gk20a_read_ptimer(struct gk20a *g, u64 *value) | ||
91 | { | ||
92 | const unsigned int max_iterations = 3; | ||
93 | unsigned int i = 0; | ||
94 | u32 gpu_timestamp_hi_prev = 0; | ||
95 | |||
96 | if (!value) | ||
97 | return -EINVAL; | ||
98 | |||
99 | /* Note. The GPU nanosecond timer consists of two 32-bit | ||
100 | * registers (high & low). To detect a possible low register | ||
101 | * wrap-around between the reads, we need to read the high | ||
102 | * register before and after low. The wraparound happens | ||
103 | * approximately once per 4 secs. */ | ||
104 | |||
105 | /* get initial gpu_timestamp_hi value */ | ||
106 | gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r()); | ||
107 | |||
108 | for (i = 0; i < max_iterations; ++i) { | ||
109 | u32 gpu_timestamp_hi = 0; | ||
110 | u32 gpu_timestamp_lo = 0; | ||
111 | |||
112 | gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r()); | ||
113 | gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r()); | ||
114 | |||
115 | if (gpu_timestamp_hi == gpu_timestamp_hi_prev) { | ||
116 | *value = (((u64)gpu_timestamp_hi) << 32) | | ||
117 | gpu_timestamp_lo; | ||
118 | return 0; | ||
119 | } | ||
120 | |||
121 | /* wrap-around detected, retry */ | ||
122 | gpu_timestamp_hi_prev = gpu_timestamp_hi; | ||
123 | } | ||
124 | |||
125 | /* too many iterations, bail out */ | ||
126 | nvgpu_err(g, "failed to read ptimer"); | ||
127 | return -EBUSY; | ||
128 | } | ||
129 | |||
130 | int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) | 62 | int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) |
131 | { | 63 | { |
132 | u64 iova = nvgpu_inst_block_addr(g, bar1_inst); | 64 | u64 iova = nvgpu_inst_block_addr(g, bar1_inst); |
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h index fe1cad58..541472cd 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h | |||
@@ -25,13 +25,11 @@ | |||
25 | #include <nvgpu/types.h> | 25 | #include <nvgpu/types.h> |
26 | 26 | ||
27 | struct gk20a; | 27 | struct gk20a; |
28 | struct gpu_ops; | ||
29 | struct nvgpu_mem; | 28 | struct nvgpu_mem; |
30 | struct nvgpu_sgt; | 29 | struct nvgpu_sgt; |
31 | struct nvgpu_sgl; | 30 | struct nvgpu_sgl; |
32 | 31 | ||
33 | void gk20a_bus_isr(struct gk20a *g); | 32 | void gk20a_bus_isr(struct gk20a *g); |
34 | int gk20a_read_ptimer(struct gk20a *g, u64 *value); | ||
35 | void gk20a_bus_init_hw(struct gk20a *g); | 33 | void gk20a_bus_init_hw(struct gk20a *g); |
36 | int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); | 34 | int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); |
37 | u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem, | 35 | u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem, |
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gm20b.c b/drivers/gpu/nvgpu/common/bus/bus_gm20b.c index 3e27053a..669cb0ae 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gm20b.c +++ b/drivers/gpu/nvgpu/common/bus/bus_gm20b.c | |||
@@ -23,13 +23,10 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <nvgpu/timers.h> | 25 | #include <nvgpu/timers.h> |
26 | #include <nvgpu/bus.h> | ||
27 | #include <nvgpu/mm.h> | 26 | #include <nvgpu/mm.h> |
28 | #include <nvgpu/enabled.h> | 27 | #include <nvgpu/enabled.h> |
29 | 28 | ||
30 | #include "gk20a/gk20a.h" | 29 | #include "gk20a/gk20a.h" |
31 | |||
32 | #include "bus_gk20a.h" | ||
33 | #include "bus_gm20b.h" | 30 | #include "bus_gm20b.h" |
34 | 31 | ||
35 | #include <nvgpu/hw/gm20b/hw_bus_gm20b.h> | 32 | #include <nvgpu/hw/gm20b/hw_bus_gm20b.h> |
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gm20b.h b/drivers/gpu/nvgpu/common/bus/bus_gm20b.h index 961b906a..1700a7e7 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gm20b.h +++ b/drivers/gpu/nvgpu/common/bus/bus_gm20b.h | |||
@@ -22,8 +22,8 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef _NVGPU_GM20B_BUS | 25 | #ifndef NVGPU_GM20B_BUS |
26 | #define _NVGPU_GM20B_BUS | 26 | #define NVGPU_GM20B_BUS |
27 | 27 | ||
28 | struct gk20a; | 28 | struct gk20a; |
29 | struct nvgpu_mem; | 29 | struct nvgpu_mem; |