From d71d38087ded679f60714dae3a859523a19df04f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 24 May 2018 15:25:41 -0700 Subject: gpu: nvgpu: Separate timer from bus Code touching timer registers was combined with bus code. They're two logically separate register spaces, so separate the code accordingly. JIRA NVGPU-588 Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1730893 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/bus/bus.c | 51 ---------------------- drivers/gpu/nvgpu/common/bus/bus_gk20a.c | 72 +------------------------------- drivers/gpu/nvgpu/common/bus/bus_gk20a.h | 2 - drivers/gpu/nvgpu/common/bus/bus_gm20b.c | 3 -- drivers/gpu/nvgpu/common/bus/bus_gm20b.h | 4 +- 5 files changed, 4 insertions(+), 128 deletions(-) delete mode 100644 drivers/gpu/nvgpu/common/bus/bus.c (limited to 'drivers/gpu/nvgpu/common/bus') diff --git a/drivers/gpu/nvgpu/common/bus/bus.c b/drivers/gpu/nvgpu/common/bus/bus.c deleted file mode 100644 index 3889512a..00000000 --- a/drivers/gpu/nvgpu/common/bus/bus.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include - -#include "gk20a/gk20a.h" - -int nvgpu_get_timestamps_zipper(struct gk20a *g, - u32 source_id, u32 count, - struct nvgpu_cpu_time_correlation_sample *samples) -{ - int err = 0; - unsigned int i = 0; - - if (gk20a_busy(g)) { - nvgpu_err(g, "GPU not powered on\n"); - err = -EINVAL; - goto end; - } - - for (i = 0; i < count; i++) { - err = g->ops.bus.read_ptimer(g, &samples[i].gpu_timestamp); - if (err) - return err; - - samples[i].cpu_timestamp = nvgpu_hr_timestamp(); - } - -end: - gk20a_idle(g); - return err; -} diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c index 9f0446c6..532fc9c6 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c @@ -28,7 +28,6 @@ #include "bus_gk20a.h" #include -#include void gk20a_bus_init_hw(struct gk20a *g) { @@ -45,7 +44,7 @@ void gk20a_bus_init_hw(struct gk20a *g) void gk20a_bus_isr(struct gk20a *g) { - u32 val, save0, save1, fecs_errcode = 0; + u32 val; val = gk20a_readl(g, bus_intr_0_r()); @@ -53,80 +52,13 @@ void gk20a_bus_isr(struct gk20a *g) bus_intr_0_pri_fecserr_m() | bus_intr_0_pri_timeout_m())) { - save0 = gk20a_readl(g, timer_pri_timeout_save_0_r()); - if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) { - /* - * write & addr fields in timeout_save0 - * might not be reliable - */ - fecs_errcode = gk20a_readl(g, - timer_pri_timeout_fecs_errcode_r()); - } - - save1 = gk20a_readl(g, timer_pri_timeout_save_1_r()); - nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x ADR 0x%08x " - "%s DATA 0x%08x ", - val, - timer_pri_timeout_save_0_addr_v(save0) << 2, - timer_pri_timeout_save_0_write_v(save0) ? - "WRITE" : "READ", save1); - - gk20a_writel(g, timer_pri_timeout_save_0_r(), 0); - gk20a_writel(g, timer_pri_timeout_save_1_r(), 0); - - if (fecs_errcode) { - nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode); - if (g->ops.priv_ring.decode_error_code) - g->ops.priv_ring.decode_error_code(g, - fecs_errcode); - } - + g->ops.ptimer.isr(g); } else { nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val); } gk20a_writel(g, bus_intr_0_r(), val); } -int gk20a_read_ptimer(struct gk20a *g, u64 *value) -{ - const unsigned int max_iterations = 3; - unsigned int i = 0; - u32 gpu_timestamp_hi_prev = 0; - - if (!value) - return -EINVAL; - - /* Note. The GPU nanosecond timer consists of two 32-bit - * registers (high & low). To detect a possible low register - * wrap-around between the reads, we need to read the high - * register before and after low. The wraparound happens - * approximately once per 4 secs. */ - - /* get initial gpu_timestamp_hi value */ - gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r()); - - for (i = 0; i < max_iterations; ++i) { - u32 gpu_timestamp_hi = 0; - u32 gpu_timestamp_lo = 0; - - gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r()); - gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r()); - - if (gpu_timestamp_hi == gpu_timestamp_hi_prev) { - *value = (((u64)gpu_timestamp_hi) << 32) | - gpu_timestamp_lo; - return 0; - } - - /* wrap-around detected, retry */ - gpu_timestamp_hi_prev = gpu_timestamp_hi; - } - - /* too many iterations, bail out */ - nvgpu_err(g, "failed to read ptimer"); - return -EBUSY; -} - int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) { u64 iova = nvgpu_inst_block_addr(g, bar1_inst); diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h index fe1cad58..541472cd 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h @@ -25,13 +25,11 @@ #include struct gk20a; -struct gpu_ops; struct nvgpu_mem; struct nvgpu_sgt; struct nvgpu_sgl; void gk20a_bus_isr(struct gk20a *g); -int gk20a_read_ptimer(struct gk20a *g, u64 *value); void gk20a_bus_init_hw(struct gk20a *g); int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem, diff --git a/drivers/gpu/nvgpu/common/bus/bus_gm20b.c b/drivers/gpu/nvgpu/common/bus/bus_gm20b.c index 3e27053a..669cb0ae 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gm20b.c +++ b/drivers/gpu/nvgpu/common/bus/bus_gm20b.c @@ -23,13 +23,10 @@ */ #include -#include #include #include #include "gk20a/gk20a.h" - -#include "bus_gk20a.h" #include "bus_gm20b.h" #include diff --git a/drivers/gpu/nvgpu/common/bus/bus_gm20b.h b/drivers/gpu/nvgpu/common/bus/bus_gm20b.h index 961b906a..1700a7e7 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gm20b.h +++ b/drivers/gpu/nvgpu/common/bus/bus_gm20b.h @@ -22,8 +22,8 @@ * DEALINGS IN THE SOFTWARE. */ -#ifndef _NVGPU_GM20B_BUS -#define _NVGPU_GM20B_BUS +#ifndef NVGPU_GM20B_BUS +#define NVGPU_GM20B_BUS struct gk20a; struct nvgpu_mem; -- cgit v1.2.2