diff options
author | Philip Elcan <pelcan@nvidia.com> | 2018-08-29 15:46:12 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-07 00:33:50 -0400 |
commit | 7f8226887c28267d3c2351692d4429ead1e17695 (patch) | |
tree | aa09c45e496b058044c9d9a94c94d9922c572285 /drivers/gpu/nvgpu/clk/clk_freq_controller.h | |
parent | 0e58ebaae13dd59b6aba5297f898e7c89fcd2742 (diff) |
gpu: nvgpu: cleanup return types for MISRA 10.3
This is a big cleanup of return types across a number of modules in the
nvgpu driver. Many functions were returning u32 but using negative
return codes. This is a MISRA 10.3 violation by assigning signed values
to a u32.
JIRA NVGPU-647
Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810743
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_freq_controller.h')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_freq_controller.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.h b/drivers/gpu/nvgpu/clk/clk_freq_controller.h index 1b8a24c9..659b75d5 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.h +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -78,7 +78,7 @@ struct clk_freq_controllers { | |||
78 | void *pprereq_load; | 78 | void *pprereq_load; |
79 | }; | 79 | }; |
80 | 80 | ||
81 | u32 clk_freq_controller_sw_setup(struct gk20a *g); | 81 | int clk_freq_controller_sw_setup(struct gk20a *g); |
82 | u32 clk_freq_controller_pmu_setup(struct gk20a *g); | 82 | int clk_freq_controller_pmu_setup(struct gk20a *g); |
83 | 83 | ||
84 | #endif | 84 | #endif |