From 7f8226887c28267d3c2351692d4429ead1e17695 Mon Sep 17 00:00:00 2001 From: Philip Elcan Date: Wed, 29 Aug 2018 15:46:12 -0400 Subject: gpu: nvgpu: cleanup return types for MISRA 10.3 This is a big cleanup of return types across a number of modules in the nvgpu driver. Many functions were returning u32 but using negative return codes. This is a MISRA 10.3 violation by assigning signed values to a u32. JIRA NVGPU-647 Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c Signed-off-by: Philip Elcan Reviewed-on: https://git-master.nvidia.com/r/1810743 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/clk/clk_freq_controller.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/clk/clk_freq_controller.h') diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.h b/drivers/gpu/nvgpu/clk/clk_freq_controller.h index 1b8a24c9..659b75d5 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.h +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -78,7 +78,7 @@ struct clk_freq_controllers { void *pprereq_load; }; -u32 clk_freq_controller_sw_setup(struct gk20a *g); -u32 clk_freq_controller_pmu_setup(struct gk20a *g); +int clk_freq_controller_sw_setup(struct gk20a *g); +int clk_freq_controller_pmu_setup(struct gk20a *g); #endif -- cgit v1.2.2